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| User Papers and Presentations |
| AMS and More |
Embedded DRAM Design / Behavioral Model Verification using ESPCV - Symbolic Simulation
Author(s): Antarpreet Singh, Shailendra Sharad, Manish Kumar Karna [STMicroelectronics Inc.] |
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Functional Validation of Memory - A Novel Approach
Author(s): Minakshi Das, Raghu Kodali [ARM] |
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Reducing Library Design Effort with Cadabra Layout Automation (1st Place - Best Paper, AMS)
Author(s): Saroj Kumar Satapathy, Pappu Satyanarayana [LSI Corporation], Vishnu Kanchi [Synopsys] |
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Transistor Level Extraction and Spice Analysis of Complex Clock Distribution System for 48 Channel 2.5Gbps PCIe SerDes
Author(s): Shrikrishna Mehetre, Prem Kishor, Chander Pal [Open-Silicon] |
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| Physical Design |
Advanced Low-Power and Optimization Techniques for MCMM Designs using ICC
Author(s): Narsimha Reddy Kodur, Gaurishankar Prafulla Gaikwad [AMD] |
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An ICC RP Based Flow to Attain the Best Area and Frequency for a Large 45nm IP Core
Author(s): Anirban Saha, Ravindra Sarda, Vishal Usapkar, Sreeram Chandrasekar, Yogendra Shukla [Texas Instruments] |
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Automatic Block Size Reduction With IC Compiler MinChip Technology
Author(s): Vineet Gupta, Abhishek Goel, Naveen Raina [STMicroelectronics] |
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Design of a High-Performance Processor in 45nm technology with ICCompiler
Author(s): Ananth Somayaji, Amit Jain, Abhishek Mishra, Sudipto Sarkar [Texas Instruments], Harissh Swaminathan [Synopsys] |
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Hierarchical Implementation of Cortex-A9 MPCore Multicore Processor with Galaxy Platform (1st Place - Best Paper, Physical Design)
Author(s): Saran Kumar Seethapathi, Arvind Kumar Sharma, Rahoul Varma [ARM], Subrata Sen [Synopsys] |
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Hierarchical Metal-Via Fill based on Configurable Fill Grid
Author(s): Dibyendu Goswami, Swami Gangadharan, Albert Holguin [Intel] |
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Leveraging MCMM and Hierarchical ILM of ICC to get optimal QOR and turn around time in 65nm large SOC
Author(s): Biswajit Patra [Qualcomm], Swapnil Garge [Synopsys] |
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| Sign Off |
Deploying NanoTime as the Next Generation Transistor-Level STA
Author(s): BhaaRathe Mallaiah Gowder, Krishnamachary Prathapuram, Sangeetha Bhanuvikraman, Vinod Kumar Reddy [KPIT Cummins] |
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Going Beyond the Milli-Volts of IRdrop
Author(s): Amit Basandrai, Dhori Kedar [STMicroelectronics], Rakesh Shenoy [Synopsys] |
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Methodology to Enable Fast and Efficient Crosstalk Closure for Large SOCs
Author(s): Chirag Gupta, Soujanna Sarkar [Texas Instruments] |
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Taping Out Very Large 65nm ASIC Designs in Affordable TAT using StarRCXT, PrimeTime, Hercules (1st Place - Best Paper, Sign-Off)
Author(s): K. A. Rajagopal, Thenappan Meyyappan, Ramesh Guzar, Suravi Bhowmik, Sabyasachi Sengupta [Texas Instruments] |
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Using DMSA for ReducingTiiming-ECO Iterations
Author(s): Vandana Dubbaka, Sridevi Warrier [Analog Devices] |
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Variation Aware Analysis using PrimeTime-VX
Author(s): Arvind N V, Ananth Somayaji, Abhishek Mishra, Ajoy Mandal, Hariprasad TT, Sandeep P [Texas Instruments] |
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Voltage Aware Static Timing Analysis : Need and Benefits
Author(s): Prashant Soraiyur, Neeraj Mishra [Texas Instruments] |
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| Synthesis and Test |
A Modular Implementation of DFTCMax for Ensuring Low Area Overheads and High Test Quality
Author(s): Rajesh Tiwari, Srivaths Ravi [Texas Instruments], Mohammed Hussain, Kuba Smieciuszewski [Synopsys] |
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Detection of High Resistance Bridge Defects using Slack Based Dynamic Bridging Fault Model
Author(s): Dibakar Gope [Birla Institute of Technology & Science], Srinivasulu Alampally, Srinivas Kumar Vooka, Rubin A. Parekhji [Texas Instruments] |
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Integrated Flow For Achieving Test Time Quality Balance
Author(s): Prasanth V, Prashant Kulkarni, Srinivas Vooka [Texas Instruments], Neha Mahajan [Thapar University] |
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Leveraging Formal Equivalence Methods for Fast and Accurate Power Estimation
Author(s): Jithendra Srinivas, Jairam S, Udayakumar H [Texas Instruments], Vikram Avaral [Synopsys] |
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Low Power DFT in Low Power Designs
Author(s): Swapnil Bahl, Rajiv Sarkar, Akhil Garg [STMicroelectronics] |
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Multiple Compressor for a Multi-Million gate Design
Author(s): Triveni Rachapalli, Sivakumar Katta [Qualcomm], Daryl Pereira, Paul Micheletti [Synopsys] |
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Register Cloning For Accelerated Design Closure (1st Place - Best Paper, Synthesis and Test)
Author(s): Aditya Ramachandran [Open-Silicon] |
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| Verification |
Addressing the Challenges in Full Chip Power Aware Functional Verification with MVSIM
Author(s): Prabhu Bhairi, Jacob Joseph, Amol Herlekar [Texas Instruments] |
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Challenges of Built In Self Test and Repair Verification
Author(s): Santoshkumar Jinagar, Nithin D Nagar, Divya Jayasree [IBM] |
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Establishing a Methodology for Early Validation of Multi Voltage RTL Designs
Author(s): Arijit Mukhopadhyay [Intel Corporation], Ajay Krishna Thiriveedhi, CV Sesha Sai Kumar [Synopsys] |
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Packet Based Verification Environment Using SV and VMM
Author(s): Ravi Kumar, Raman Kumar [Analog Devices] |
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SoC Gate Level Simulations (GLS) Cycle Time Reduction – Simulation Flow Enablers
Author(s): Rajat Sagar, Rama Kowsalya, Ashutosh Tiwari [Texas Instruments] |
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SystemVerilog: From Device Modelling to Emulation (1st Place - Best Paper, Verification)
Author(s): Yogesh Mittal [TranSwitch Corporation] |
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Transitioning a Platform Verification Environment to SystemVerilog
Author(s): Anand Shirahatti, Nitin Agrawal, Rakshit Singhal, Sankara Narayanan R N [NVIDIA] |
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Voltage Aware Static Rule Checks for Power Managed Designs
Author(s): Parthasarathy Narasimhan, Vaibhav Marathe,Chandramohan Vageesan [Cypress Semiconductor] |