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| User Papers and Presentations |
| Physical Design and Sign-off |
Accurate Gate-Level Power-Estimation in Primetime-PX using Vectors Generated from RTL Simulation
Author(s): Shitanshu Tiwari, Soumya N, Kalpesh Shah [Texas Instruments] |
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Achieving Aggressive Design Goals for High Performance Wireless Applications using IC Compiler
Author(s): Mamatha Jayanth, Kartik Ayyar [Qualcomm] |
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Challenges in Crosstalk-Aware Hierarchical STA for Multi-Million Gate VoIP SoC (1st Place - Best Paper, Physical Design and Sign-Off)
Author(s): Aakash Agrawal, Subrangshu Das, Shailendra Dhuri, [Texas Instruments] |
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Concurrent Multi-Mode Optimizations and Multi-Supply Flow with ICC Empowers to Fight the Evils of Design
Author(s): Anil Yadav, [ST Microelectronics] |
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Dynamic IR Drop Sign-off Analysis using Prime Rail
Author(s): Deepak Kumar Arora, Abhay Kumar, Jwalant Joshipura, RakeshShenoy Panemangalore, [ST Microelctronics] |
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Implementing a High Performance 65nm Core using ICC
Author(s): Balasubramanian Rajeswaran, [Texas Instruments] |
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Increased Designer Productivity for ARM Cortex-A8 Processors
Author(s): Roma Kundu, Manmohan Loganathan [ARM Embedded Technologies Pvt. Ltd.] |
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Managing Timing Convergence Efficiently in a Mixed Design Methodology
Author(s): Anupam Rajoria, Satishchandra G Rao, [Analog Devices] |
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Multimode Multiscenario Analysis on IP Designs
Author(s): Ananth Somayaji, [Texas Instruments] |
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Physical Verification Throughput Improvement for Very Large SoCs in Sub-Wavelength Regime
Author(s): Dibyendu Goswami, Swami Gangadharan, [Intel] |
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Timing and Noise Analysis Accuracy with CCS Models
Author(s): Viswanath Ramanathan, Pavan Kumar Kaipa, [Intel] |
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| Poster Session |
Adding Whistles to Synopsys Tools using Tcl
Author(s): Puneet Goel, Ashis Maitra [Transwitch] |
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Methodology for Hierarchy Separation at Asynchronous Clock Domain Boundaries for Multivoltage Optimization using Design Compiler
Author(s): Alok Anand, Sajish Sajayan [Texas Instruments] |
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Verifying an Image Processing System using VMM
Author(s): Ajeetha Kumari, S Naresh Kumar, Govind Bagath Singh V [Contemporary Verification Consultants Pvt Ltd.] |
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| Synthesis & Test |
A Novel ILM Based SoC Synthesis Strategy Using Unified Constraints
Author(s): Soujanna Sarkar, Paresh Joshi, Vasudev Sinari, [Texas Instruments] |
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Collaborative and Innovative DFT for "Pushing-the-envelope" Designs
Author(s): C. P. Ravikumar [Texas Instruments], Mohammed Hussain, Sumitha Krishnamurthi [Synopsys] |
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Concurrent Fault Detection: The New Paradigm for Compacted Test Vectors
Author(s): Srinivasulu Alampally, Srinivas Kumar Vooka [Texas Instruments], Jais Abraham, Satish Panigatti [InnoDes Solutions Pvt. Ltd] |
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Correlation of Synthesis and Layout: Is DC-T the Solution?
Author(s): V. Parimala, [Texas Instruments] |
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DC-Topographical for Structured-ASIC
Author(s): Varun Jindal, [ST Microelectronics] |
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Dynamic Shift Frequency Scaling Of ATPG Patterns (1st Place - Best Paper, Synthesis and Test)
Author(s): Aditya Ramachandran [Open-Silicon Research Private Limited] |
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Hierarchical Adaptive Scan Synthesis for Multi-Million Gate Designs
Author(s): Prasanna Kaliamoorthy, Kapil Kothari, [Open-Silicon Research Private Limited] |
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How Formal Verification can Become Bottleneck After Successful Synthesis?
Author(s): Swapnil Bahl, Atul Arora, Sabyasachi Das, Mohinder Vij [ST Microelectronics] |
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Increased Designer Productivity for ARM Cortex-A8 Processors
Author(s): Roma Kundu, Manmohan Loganathan [ARM Embedded Technologies Pvt. Ltd.] |
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Physical Aware Synthesis with DC Topographical
Author(s): Sivaprasad Embanath [MIMOS Berhad] |
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Small Delay Defect Testing in DSM Technologies- Needs and Considerations
Author(s): Srinivasulu Alampally, Prasanth V, Rajesh Tiwari, Sumitha Krishnamurthi, [Texas Instruments] |
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| Verification & AMS |
A High-Performance Timing Simulation Methodology for Multi-Processor SoCs
Author(s): Bhaskar J Karmakar, Ish Dham, Sivaprasad Acharya [Texas Instruments] |
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A Methodology for Generating Interface Timing Models of Complex Custom Designs using Nanosim & Star RC
Author(s): Satishchandra Rao, Vijaykishan N, Vinoth Kumar, Jayakrishnan V, Srijith Varma [Analog Devices] |
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An Efficient Approach for Verifying a Pipelined Processor
Author(s): Manmohan Singh, Srikanth Muralidharan, Sunil Parmar, V. Ranjith Kumar, Praneet Dixit [Qualcore Logic] |
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Analysis of Sustainable Wait Latencies for a Host Interface Module using Magellan
Author(s): Prasenjit Basu, Raj S Mitra, Sarbadipta Datta [Texas Instruments] |
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Complex Signal Integrity Simulations for GPIOs using HSIM Hierarchical Flow (1st Place - Best Paper, AMS)
Author(s): Rakesh Sawant, Nagarathinam Senthil [Qualcomm] |
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Constraint Based Random Verification Methodology for the Generic Designs
Author(s): Swapnil Sapre, Hitesh Kumar Mishra [Freescale] |
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Functional Verification of SPI3 TX Link Core using VMM
Author(s): Ramamohan Sriram, Shreedevi C, Archana Gupta, Debajyoti Mukherjee [Wipro Technologies] |
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Multiple Voltage Domains Testing Using Functional Simulation
Author(s): Sukruth Pattanagiri, Sivakumar R [Analog Devices] |
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RAL Demystified: A Fast Path to Smart Control Plane Verification
Author(s): Gaurav Jain, Yogesh Mittal, Parag Goel [Transwitch] |
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Spice Acceleration by Introduction of HSIM in Design Cycle for Analog Circuits
Author(s): Anuj Gupta [ST Microelectronics], Rakesh Shenoy [Synopsys] |
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Usage of VMM to Address Gigabit Switch Verification Challenges (1st Place - Best Paper, Verification)
Author(s): Yogesh Mittal, Neeraj Chandak, Parag Goel [Transwitch] |
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VMM Based Verification Environment for Telecom Designs
Author(s): Paul Kaunds, Sowmya Sullia,Asha Rai [Kacper Technologies] |