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| User Papers and Presentations |
| A1 Tutorial & User - Design for Test |
Massive Test Cost Reduction by Advanced SCAN Testing (Technical Committee Award Honorable Mention)
Author(s): Claus Kuntzsch, Malav Shah [Texas Instruments] Nikolaus Mittermaier [Synopsys, GmbH] |
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| A2 Tutorial & User - Physical Implementation - Routing Technology - Zroute |
Deploying ICC Zroute for Advanced Node Testchip Design
Author(s): Ulrich Hensel, Rainer Mann, Steffen Seeling [GlobalFoundries] |
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| A3 Tutorial & User - Functional Verification |
"What gets measured gets done" - Predictable verification with VMM Planner (Technical Committee Award)
Author(s): Tobias Leisgang [Texas Instruments] |
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Exploiting the TLM-2 Features of VMM 1.2
Author(s): John Aynsley [Doulos Ltd.] |
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| A4 User - AMS Verification |
Effective Post Layout Verification of AMS Designs at 28nm by means of StarRC Extracted Views (2nd Place - Best Paper)
Author(s): Hendrik Mau [GlobalFoundries] |
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PLL Characterization using HSPICE RF in Custom Designer Environment
Author(s): Jan Sysr [CertiCon], Saad Jabir [Synopsys, GmbH] |
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Usage of SNPS XA in IFAT DC Villach
Author(s): Roland Lengfeldner [Infineon Technologies] |
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| A5 Tutorial & User - Low Power Verification |
Low Power Verification with MVRC on a Hierarchical UPF Design
Author(s): Stefan Rolf [Infineon Technologies] |
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| A6 User & Tutorial - Saber System Simulation - I |
Frameway - The Interface for CR5000 Systemdesigner and Saber
Author(s): Markus Röder [Bosch Engineering GmbH] |
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Seamless Transition from Functional SysML Specification to Virtual Prototyping using Saber
Author(s): Joerg Christoffers, Wladimir Schamai [EADS Innovation Works] |
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| B1 Tutorial & User - Logic Synthesis |
Floorplan-Based SoC Synthesis
Author(s): Fredrik Angsmark [STEricsson] |
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| B2 Tutorial & User - IC Design Implementation: Feasibility&Dirty Netlist Handling |
Experiences with ICC Black Box Flow (1st Place - Best Paper)
Author(s): Farid Labib, Herbert Preuthen [LSI, Corp.] |
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| B3 User - Functional Verification |
Do more, worry less - Adding more abstraction to the USB DesignWare VIP
Author(s): Florin Rosca, Mihai Tecuceanu [NoBug Consulting], Tobias Leisgang [Texas Instruments] |
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Hitchhikers Guide to Structural and Functional Coverage Merging and Mapping with VCS, SystemVerilog and VMM (3rd Place - Best Paper)
Author(s): Jacob Andersen, Benny Andersson, Peter Jensen [SyoSil ApS] |
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Reusable Functional Clock Verification
Author(s): Joachim Geishauser, Glen Guo, David Li, Alexander Schillings [Freescale Semiconductors] |
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Standardizing VMM Performance Analyzer Implementations Across VMM Testbenches
Author(s): Jacob Andersen, Peter Jensen, Michael Kappelhøj Andersen [SyoSil Consulting] |
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| B4 Tutorial & User - Custom Designer Infrastructure: Process Development Kits (PDKs) |
Building an Interoperable Process Design Kit for a "State of the Art" Mixed-Signal CMOS Technology Platform
Author(s): Bernd Fischer-Krellenberg [Lfoundry] |
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Developing PDK Kits for Custom Designer
Author(s): Wolfgang Grimm [X-FAB] |
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| B6 User - Saber System Simulation - II |
Data Documentation Through External tcl Packages Combined with Saber
Author(s): Henning Johnsen [Danfoss Drives] |
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Model Generation using Worst Case Analysis Tool
Author(s): Stefan Heimburger [Bosch Engineering GmbH] |
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Signal Integrity Evaluation on Aeronautic FlexRay Networks
Author(s): Christoph Heller [EADS Innovation Works] |
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| C1 User & Tutorial - Signoff |
Using Primetime DMSA for Timing Analysis, Power Recovery and Hold Time Fixing for a Multi-Million Gate, Multi-Mode ASIC Design
Author(s): Satinder Singh [LSI, Corp.] |
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| C3 User & Tutorial - Low Power Implementation |
The Advent of UPF
Author(s): Serge Durand, Faisal Suleman - [Semtech Neuchatel SA] |
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| C4 User & Tutorial - Design Successes with Custom Designer |
Integrated Actuator Control for Mobile Camera Applications using Custom Designer Analog/Mixed-Signal Design Flow
Author(s): Frank Kronmueller [Digital Imaging Systems] |
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| Tutorials |
| A1 Tutorial & User - Design for Test |
You Have the Power to Test! | Power-Aware Test Solution
Author(s): Nikolaus Mittermaier [Synopsys, GmbH] |
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| A2 Tutorial & User - Physical Implementation - Routing Technology - Zroute |
ICC Zroute Recap: ST Real Life Implementation Example
Author(s): Frank Schlegel [Synopsys, GmbH] |
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| A3 Tutorial & User - Functional Verification |
DVE - What you Need to Know about VCS' Advanced Debugging and Visualization Environment
Author(s): Jörg Richter [Synopsys, GmbH] |
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| A5 Tutorial & User - Low Power Verification |
The Power of Low Verification
Author(s): Michael Confal [Synopsys, GmbH] |
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| A6 User & Tutorial - Saber System Simulation - I |
Design for Reliability
Author(s): Andre Jennert [Synopsys, GmbH] |
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| B1 Tutorial & User - Logic Synthesis |
Galaxy RTL: Design Compiler Family 2010.03 Links to Physical Design and Other Advanced Features
Author(s): Rolf Ferner [Synopsys, GmbH] |
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| B2 Tutorial & User - IC Design Implementation: Feasibility&Dirty Netlist Handling |
IC Compiler Feasibility, Planning and Implementation
Author(s): Rainer Hadwiger [Synopsys, GmbH] |
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| B4 Tutorial & User - Custom Designer Infrastructure: Process Development Kits (PDKs) |
Custom Designer Update
Author(s): [Synopsys, GmbH] |
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| B5 Tutorial - High Level Syntheses |
Synphony: High Level Synthesis for FPGA and ASIC
Author(s): Pierluigi LoMuzio [Synopsys, GmbH] |
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| C1 User & Tutorial - Signoff |
Galaxy Constraints Analyzer: Constraints Debugging Made Easy
Author(s): Gernot Gall [Synopsys, GmbH] |
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| C2 Tutorial - IC Design Implementation: Large Design Handling |
IC Compiler Exploration & onDemand Loading Flow for Ultra Large Design
Author(s): Rainer Hadwiger [Synopsys, GmbH] |
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| C3 User & Tutorial - Low Power Implementation |
Best Practices for Multi-Voltage Implementation with UPF
Author(s): Knut Dalkowski [Synopsys, GmbH] |
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| C4 User & Tutorial - Design Successes with Custom Designer |
Efficient Analog IP Migration: A migration experience from Synopsys MSIP
Author(s): [Synopsys, GmbH] |
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| C5 Tutorial - Prototyping |
Speedup System Development Schedule by Adding Rapid Prototyping to your Flow
Author(s): Robert Eichner [Synopsys, GmbH] |
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| C6 Tutorial - Saber Product Updates |
Product Update and Future Direction
Author(s): Lee Johnson [Synopsys, GmbH] |
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Robust Design of Wiring Harness Systems in E³.series with E³.SaberFrameway
Author(s): Martin Santen [Zuken] |
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SaberRD - Robust Design for Desktop Simulation
Author(s): Thorsten Gerke [Synopsys, GmbH] |