SNUG France 2011 Proceedings

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User Papers and Presentations
A1 - Low-Power Implementation and Constraint Checking
Efficient Constraints Debug using Galaxy Constraints Analyzer
Author(s): Gianni Lazzari [STMicroelectronics], Alfredo Conte [Synopsys Italy]
PaperPresentation

Multi-supply Multi-voltage UPF RTL-to-Backend Flow
Author(s): Estelle Fazilleau, Christophe Robichon [Atmel Corporation]
PaperPresentation

A2 - RTL Verification - Testbench Automation
Forks that Cut It: Applications for SystemVerilog Dynamic Processes
Author(s): Bertrand Cuzeau [Doulos]
PaperPresentation

A3 - Advanced Physical Design Flows
Efficient Standard Cell Characterization for GLOBALFOUNDRIES 28nm Technologies using a Star-RC and Liberty-NCX-based Flow (2nd Place - Best Paper)
Author(s): Robert Siegmund, Ben Gullette, Andre Schulze [GLOBALFOUNDRIES]
PaperPresentation

How to Reach High Performance with Tiempo Clockless Designs Using PrimeTime and ICC
Author(s): Nicolas Leblond [Tiempo S.A.S.]
PaperPresentation

A4 - Design for Test and ATPG I
Simplifying the Multi Fault ATPG Flow with Persistent Fault Model
Author(s): Paolo Cavenaghi [STMicroelectronics], Salvatore Talluto [Synopsys Italy]
PaperPresentation

Some Experiences of DFTMax Serializer on Two Complex Chips
Author(s): Paul Armagnat [STMicroelectronics], Julien Pouget [ST-Ericsson]
PaperPresentation

Using Custom OCC with TetraMax for At-speed Transition Fault Testing and Small Delay Defect
Author(s): Cedric Papon [Parrot], Philippe Rossant [Synopsys France]
PaperPresentation

A5 - AMS and Full Custom Design
ICC-Custom Designer Link to Improve the Product Development Cycle Time! (Technical Committee Award)
Author(s): Christelle Leherpeur [ST Microelectronics France]
PaperPresentation

A6 - High Level Synthesis and FPGA Vision
Design of Evolutionary H264 Codec Using Synphony C Compiler High Level Synthesis
Author(s): José Sanches, Olivier Schneider [ST-Ericsson France]
PaperPresentation

High Level Synthesis of High Data Rate Metrology Wireless Sensor Network for Aerospace Applications
Author(s): Julien Henaut, Daniela Dragomirescu, Robert Plana [LAAS]
PaperPresentation

B1 - Back-End Integration to Synthesis
Accelerating Design Closure with Synthesis Physical Guidance (SPG) Flow - ST-Ericsson
Author(s): Fatima-Ezahra Najmeddine, Latifa Ouizat, Moulay Lekbir Ait Moulay Cherif [ST-Ericsson], Hervé Raffard, Philippe Rossant [Synopsys France]
PaperPresentation

How to Solve Congestion Issues at RTL Level Using Design Compiler Graphical
Author(s): Salima El Makhtari [ST-Ericsson], Philippe Rossant [Synopsys France]
PaperPresentation

B2 - Low-Power Verification
Signoff Static Low Power Verification on Large Design using MVRC
Author(s): Hatem Ayari [ST-Ericsson]
PaperPresentation

UPF Power State Table Verification Methodology using MVSIM (Technical Committee Award Honorable Mention)
Author(s): Christophe Clavel [ST-Ericsson]
PaperPresentation

B3 - Physical Design: Timing Closure
Primetime as an Implementation Tool
Author(s): Frank Vaneerdewegh [St-Ericsson The Netherlands]
PaperPresentation

B4 - Design for Test and ATPG II
Manufacturing STIL Patterns Validation with MAX Test Bench Feature
Author(s): Cosimo Torelli [STMicroelectronics Italy], Salvatore Talluto, Alfredo Conte [Synopsys Italy]
PaperPresentation

Reconfigurable Wrapper Test Access Mechanism (TAM) in a Core Based DFT Strategy to Save Interconnect Test Time (3rd Place - Best Paper)
Author(s): Isabelle Delbaere, Caroline Carin and Christophe Eychenne [ST-Ericsson]
PaperPresentation

Techniques for Achieving High Test Quality using DFT Compiler/DFTMAX™ Compression and TetraMAX
Author(s): Derya Eker [ST-Ericsson Elndhoven]
PaperPresentation

B5 - AMS Design and Verification
Creation of an Embedded Temperature Sensor for Low Geometry Nodes using the Custom Designer Mixed-Signal Design Flow
Author(s): Stephen Crosher, Neil Roberts [Moortec Semiconductor Limited]
PaperPresentation

Electrical Rule Check with XA at Chip lLvel to Detect Dynamic HiZ, Current Leakage and Overvoltage on Thin Oxides
Author(s): Vincent Vincent Bligny, François Ravatin [ST-Ericsson], Philippe Brahic [Synopsys France]
PaperPresentation

B6 - FPGA Design and Prototyping
Hardware/Software Debugging with FPGA Based Prototyping
Author(s): Gregory Prieur [ST-Ericsson]
PaperPresentation

C2 - System Level Verification
Formal Verification and Validation of High-Level Optimizations of Arithmetic Datapath Blocks
Author(s): Theo Drane [Imagination Technologies], Himanshu Jain [Synopsys]
PaperPresentation

C5 - Advanced Mixed-Signal Verification
Improve Verification Coverage of an Asynchronous Microcontroller with System Verilog - HSIM Co-simulation (1st Place - Best Paper)
Author(s): Bertrand Folco [Tiempo France]
PaperPresentation

C6 - Advanced FPGA-based Prototyping
Creating a Debugging Environment to Validate Real-time Scheduling Algorithms
Author(s): Yannick Allard, Joël Goossens, Dragomir Milojevic [ULB-PARTS Brussels, Belgium]
PaperPresentation

Publication Only
Leakage Power Optimization Flow for Low Power Designs
Author(s): Ramy Gamal [Dubai Circuit Design]
Paper

Tutorials
A1 - Low-Power Implementation and Constraint Checking
New Multi-Voltage Power Optimization Techniques to Address Power Reduction During Design Implementation
Author(s): Géraldine Avinin [Synopsys France]
Tutorial

A2 - RTL Verification - Testbench Automation
My First Testbench Using UVM
Author(s): Fabian Delguste [Synopsys France]
Tutorial

A3 - Advanced Physical Design Flows
Lynx Design System at work
Author(s): Cyrille Thomas, Fabien Pouchol [Bull]
Tutorial Customer Testimonial

A5 - AMS and Full Custom Design
Synopsys Custom Design Solution
Author(s): Guillaume Thomas [Synopsys France]
Tutorial

B3 - Physical Design: Timing Closure
Faster Multi-Scenario ECO Fixing in PrimeTime
Author(s): Eric Zann [Synopsys France]
Tutorial

B5 - AMS Design and Verification
Introducing CustomExplorer Ultra - a Comprehensive Mixed Signal Simulation Environment
Author(s): Dwayne Holst [Synopsys Inc.]
Tutorial

B6 - FPGA Design and Prototyping
Latest Synthesis Technologies and Techniques for High-Capacity FPGA Designs
Author(s): Xavier Mathes [Synopsys France]
Tutorial

C1 - Front-End Design Exploration
DC Explorer Tutorial and ST TR&D Testimonial
Author(s): Emanuele Parrinello [STMicroelectronics], Alberto Baldi [Synopsys Italy]
Tutorial Customer Testimonial

R&D Q&A Session
Author(s):
Presentation

C2 - System Level Verification
Embedded Software Driven Post-Silicon System and Power Validation using Virtual Prototypes
Author(s): Xavier Buisson [Synopsys France]
Tutorial

C3 - Hierarchical Physical Design and Exploration
IC Compiler Fast Hierarchical Design Exploration, Planning, Block Implementation and Top-Level Closure
Author(s): TBC [Synopsys]
Tutorial

C4 - Design for Test and Yield Improvement
Lowering Pattern Count in TetraMAX
Author(s): Salvatore Talluto [Synopsys Italy]
Tutorial

R&D Q&A Session
Author(s):

Volume Diagnostics: The Key to Faster Yield Ramp at Nanometer Node Technologies
Author(s): Pietro Babighian [Synopsys Italy]
Tutorial

C5 - Advanced Mixed-Signal Verification
Advanced Techniques for Mixed- Signal Verification with XA-VCS
Author(s): Philippe Brahic [Synopsys France]
Tutorial

C6 - Advanced FPGA-based Prototyping
High Capacity and Advanced FPGA-based Prototyping with HAPS
Author(s): Laurent Sol [Synopsys France]
Tutorial

Demo
B1 - Back-End Integration to Synthesis
DCG-ICC-DP Link
Author(s): Nevil Doctor [Synopsys France]
Demo

B2 - Low-Power Verification
MVSIM-NLP: Native Low-Power Simulation
Author(s): Patrick Blestel [Synopsys France]
Demo