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| User Papers and Presentations |
| A1 - Low-Power Implementation and Constraint Checking |
Efficient Constraints Debug using Galaxy Constraints Analyzer
Author(s): Gianni Lazzari [STMicroelectronics], Alfredo Conte [Synopsys Italy] |
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Multi-supply Multi-voltage UPF RTL-to-Backend Flow
Author(s): Estelle Fazilleau, Christophe Robichon [Atmel Corporation] |
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| A2 - RTL Verification - Testbench Automation |
Forks that Cut It: Applications for SystemVerilog Dynamic Processes
Author(s): Bertrand Cuzeau [Doulos] |
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| A3 - Advanced Physical Design Flows |
Efficient Standard Cell Characterization for GLOBALFOUNDRIES 28nm Technologies using a Star-RC and Liberty-NCX-based Flow (2nd Place - Best Paper)
Author(s): Robert Siegmund, Ben Gullette, Andre Schulze [GLOBALFOUNDRIES] |
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How to Reach High Performance with Tiempo Clockless Designs Using PrimeTime and ICC
Author(s): Nicolas Leblond [Tiempo S.A.S.] |
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| A4 - Design for Test and ATPG I |
Simplifying the Multi Fault ATPG Flow with Persistent Fault Model
Author(s): Paolo Cavenaghi [STMicroelectronics], Salvatore Talluto [Synopsys Italy] |
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Some Experiences of DFTMax Serializer on Two Complex Chips
Author(s): Paul Armagnat [STMicroelectronics], Julien Pouget [ST-Ericsson] |
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Using Custom OCC with TetraMax for At-speed Transition Fault Testing and Small Delay Defect
Author(s): Cedric Papon [Parrot], Philippe Rossant [Synopsys France] |
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| A5 - AMS and Full Custom Design |
ICC-Custom Designer Link to Improve the Product Development Cycle Time! (Technical Committee Award)
Author(s): Christelle Leherpeur [ST Microelectronics France] |
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| A6 - High Level Synthesis and FPGA Vision |
Design of Evolutionary H264 Codec Using Synphony C Compiler High Level Synthesis
Author(s): José Sanches, Olivier Schneider [ST-Ericsson France] |
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High Level Synthesis of High Data Rate Metrology Wireless Sensor Network for Aerospace Applications
Author(s): Julien Henaut, Daniela Dragomirescu, Robert Plana [LAAS] |
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| B1 - Back-End Integration to Synthesis |
Accelerating Design Closure with Synthesis Physical Guidance (SPG) Flow - ST-Ericsson
Author(s): Fatima-Ezahra Najmeddine, Latifa Ouizat, Moulay Lekbir Ait Moulay Cherif [ST-Ericsson], Hervé Raffard, Philippe Rossant [Synopsys France] |
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How to Solve Congestion Issues at RTL Level Using Design Compiler Graphical
Author(s): Salima El Makhtari [ST-Ericsson], Philippe Rossant [Synopsys France] |
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| B2 - Low-Power Verification |
Signoff Static Low Power Verification on Large Design using MVRC
Author(s): Hatem Ayari [ST-Ericsson] |
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UPF Power State Table Verification Methodology using MVSIM (Technical Committee Award Honorable Mention)
Author(s): Christophe Clavel [ST-Ericsson] |
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| B3 - Physical Design: Timing Closure |
Primetime as an Implementation Tool
Author(s): Frank Vaneerdewegh [St-Ericsson The Netherlands] |
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| B4 - Design for Test and ATPG II |
Manufacturing STIL Patterns Validation with MAX Test Bench Feature
Author(s): Cosimo Torelli [STMicroelectronics Italy], Salvatore Talluto, Alfredo Conte [Synopsys Italy] |
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Reconfigurable Wrapper Test Access Mechanism (TAM) in a Core Based DFT Strategy to Save Interconnect Test Time (3rd Place - Best Paper)
Author(s): Isabelle Delbaere, Caroline Carin and Christophe Eychenne [ST-Ericsson] |
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Techniques for Achieving High Test Quality using DFT Compiler/DFTMAX™ Compression and TetraMAX
Author(s): Derya Eker [ST-Ericsson Elndhoven] |
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| B5 - AMS Design and Verification |
Creation of an Embedded Temperature Sensor for Low Geometry Nodes using the Custom Designer Mixed-Signal Design Flow
Author(s): Stephen Crosher, Neil Roberts [Moortec Semiconductor Limited] |
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Electrical Rule Check with XA at Chip lLvel to Detect Dynamic HiZ, Current Leakage and Overvoltage on Thin Oxides
Author(s): Vincent Vincent Bligny, François Ravatin [ST-Ericsson], Philippe Brahic [Synopsys France] |
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| B6 - FPGA Design and Prototyping |
Hardware/Software Debugging with FPGA Based Prototyping
Author(s): Gregory Prieur [ST-Ericsson] |
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| C2 - System Level Verification |
Formal Verification and Validation of High-Level Optimizations of Arithmetic Datapath Blocks
Author(s): Theo Drane [Imagination Technologies], Himanshu Jain [Synopsys] |
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| C5 - Advanced Mixed-Signal Verification |
Improve Verification Coverage of an Asynchronous Microcontroller with System Verilog - HSIM Co-simulation (1st Place - Best Paper)
Author(s): Bertrand Folco [Tiempo France] |
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| C6 - Advanced FPGA-based Prototyping |
Creating a Debugging Environment to Validate Real-time Scheduling Algorithms
Author(s): Yannick Allard, Joël Goossens, Dragomir Milojevic [ULB-PARTS Brussels, Belgium] |