SNUG France 2009 Proceedings

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Complete Proceedings


User Papers and Presentations
A1 - RTL Synthesis
DC-G Evaluation on a Full Chip Device
Author(s): Giuseppe Fornaciari [ST-CCI-Printer]
Presentation

Synthesis strategies to Enable Accurate Critical Path Selection in Nanometer Technologies
Author(s): Bettina Rebaud [CEA-LETI]
Presentation

A2 - Physical Implementation with IC Compiler
Multimode Multicorner Optimization on 45nm IP Using ICC
Author(s): Eric Ponsot [Texas Instruments]
Presentation

Zroute Usage on High Density ARM IPs Implementations
Author(s): Alain Sermesse [ARM, Inc.]
Presentation

A3 - Analog Mixed-Signal Verification Methodologies
Mixed-Signal Integration Methodology from IP to SoC
Author(s): Patrice Vado, Mghith Mehdi [Texas Instruments]
Presentation

Smart AMS SoC Verification Flow with HSIMplus, XA & Spice Explorer
Author(s): Alessandro Valerio, Pierluigi Daglio, Luca Buratti, Claudia Castelli, Sergio Pelagalli [STMicroelectronics]
Presentation

A4 - SystemVerilog Testbench
SystemVerilog Verification: Ramping-up from IP, through Subsystem, to Chip Level
Author(s): Fabien Camus, Jerome Bombal [Texas Instruments]
Presentation

VIP-VMM Based NoC Verification Flow
Author(s): Carlo Spitale [Arteris]
Presentation

B1 - Test
Low-Power Oriented Volume Diagnosis on Yield Losses Depending on Chain Failures
Author(s): Olivia Riewer, Davide Appello [STMicroelectronics], Salvatore Talluto [Synopsys, Inc.]
Presentation

Simulation-Based Transition Fault Flow
Author(s): Patrick Richier [ST-Ericsson]
Presentation

TetraMAX Power Aware ATPG Correlation Study with PrimeTime-PX
Author(s): Saverio Graniello, Swapnil Bahl, Akhil Garg, Roberto Mattiuzzo, Matthieu Sautier [STMicroelectronics], Alfredo Conte, Salvatore Talluto [Synopsys, Inc.]
Presentation

B2 - Sign Off
Variation-Aware Analysis Using PrimeTime-VX
Author(s): Nicolas Verkinderen, Arvind NV, Ajoy Mandal, Hariprasad TT, Sandeep P, Ananth Somayaji, Abhishek Misra, David Colin [Texas Instruments]
Presentation

B3 - Analog Full Custom Design with Custom Designer
Enabling Asynchronous Design with Standard Layout Tools
Author(s): Christophe Scarabello [Tiempo]
Presentation

B4 - Low-Power Verification
MVSIM Experience on Next Generation Wireless Digital SoC
Author(s): Frederic Hunsinger [ST-Ericsson]
Presentation

C2 - Physical Implementation with IC Compiler
High Performance IP Implementation with IC Compiler
Author(s): Arnaud Rayer, Frederic Nyer [STMicroelectronics], Jean-Hugues Bosset [ST-Ericsson]
Presentation

ICC Experience on Multi Voltage and Reduced Metal Stack Design
Author(s): Daniela Di Giovanni, Dominico Arena [STMicroelectronics], Giuseppe Contarino [Synopsys, Inc.]
Presentation

C3 - Transistor Level Advanced Verification
Advancements in Smart Power Applications Verification with XA
Author(s): Branimir Ivetic, Claudio Vignati, Lyes Djama [STMicroelectronics], Carlo Borromeo [Synopsys]
Presentation

Top-Down Electrical Verification of Mixed-Signal Power Management Circuits with HSIM CircuitCheck
Author(s): Vincent Bligny [ST-Ericsson]
Presentation

C4 - System and Prototyping
FPGA-Based SoC HDTV Prototyping Methodology with the Confirma Platform
Author(s): Philippe Damalix, Samuel Fournier, Bruno Denis, Laurent Chalet [STMicroelectronics]
Presentation

OSCI TLM2 Based Virtual Platforms: An Interoperability Trial between ST TAC Platform and Synopsys DesignWare System-Level Library
Author(s): Laurent Maillet-Contoz [STMicroelectronics]
Presentation

Tutorials
B2
Faster Timing Closure in a Multi-Scenario World
Author(s):
Tutorial

B3
Synopsys' Custom Design Solution
Author(s):
Tutorial

B4
Methodology for Successful Verification of Low Power Designs
Author(s):
Tutorial

C1
Using DC-G to Accelerate Design Closure
Author(s):
Tutorial