SNUG Canada 2013 Proceedings

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Complete Proceedings


User Papers and Presentations
A1 User Session: Performance and Regression Management
FPGA Continous Integration with Jenkins (2nd Place - Best Paper)
Author(s): Martin d’Anjou - Ciena
PaperPresentation

SoC Simulation Performance - Take a Second Look at Your VCS Setup
Author(s): Kendall Chan - Advanced Micro Devices, Inc.
PaperPresentation

A3 User & Tutorial Session: Lynx and Signoff Driven Timing Closure
I Love Lynx
Author(s): Vincent Rowley - Semtech Canada Corporation
PaperPresentation

B1 User Session: Reuse & Low Power Verification
Test Driven Design: Unit Testing... on Steroids
Author(s): Bryan Morris - Verilab
PaperPresentation

UVM-Based Vertical DV Re-use in Packet Processing ASICs (3rd Place - Best Paper)
Author(s): Karim Khordoc, Dennis Im, Lawrence Said - Cisco Systems
PaperPresentation

Verifying Crossover Signals in Low Power Simulation
Author(s): Ashwini Holla, Andy Ray, Shu-Shia Chow - Advanced Micro Devices, Inc.
PaperPresentation

B2 User & Tutorial Session: MultiSource CTS and Design Closure
The Clear Advantages of Multi-Source CTS (1st Place - Best Paper, Technical Committee Award)
Author(s): Sid Allman - Cisco Systems
PaperPresentation

B3 User & Tutorial Session: Test Using IEEE 1500 and PrimeTime Multi-scenario Technology
Design Reuse and Pin Limited Test Using IEEE 1500
Author(s): Vineet Joshi, Saman Adham - TSMC; Don Skinner - Synopsys
PaperPresentation

C3 User & Tutorial Session: Power Aware ATPG and Formality ECO
Power Aware Automatic Test Pattern Generation for ASIC Using TetraMAX
Author(s): Nirav Nanavati, Miteshwar Patel - eInfochips
PaperPresentation

Publication Only
Publish Only
An Efficient Way to Insert Test-Points at Analog Hard Macro I/Os
Author(s): Howard Lu - Semtech Corp.
Publish Only

Analysis of Active Boost vs. Passive Power Conversion in Variable Frequency Aerospace Applications
Author(s): Novica Losic - Honeywell
Publish Only

Estimating Load Torque and Moment of Inertia in an Electric Motor Drive System
Author(s): Novica Losic - Honeywell
Publish Only

Tutorials
A2 Tutorial Session: Using Concurrent Clock and Data Optimization for Improved Timing Closure
Achieving Higher Frequencies for Your Design with Early Clockgating Optimization and Comprehensive Useful Skew
Author(s): Dave Power - Synopsys
Tutorial

A3 User & Tutorial Session: Lynx and Signoff Driven Timing Closure
Signoff Driven Timing Closure with PrimeTime: Now Includes Leakage Reduction
Author(s): Steve Danielson - Synopsys
Presentation

B2 User & Tutorial Session: MultiSource CTS and Design Closure
20nm Design Closure in IC Compiler Using IC Validator in-Design
Author(s): Kevin Brelsford - Synopsys
Tutorial

B3 User & Tutorial Session: Test Using IEEE 1500 and PrimeTime Multi-scenario Technology
PrimeTime Multi-scenario Technology
Author(s): Mark Digiovanni - Synopsys
Tutorial

C1 Tutorial Session: UVM Verification IP Reuse and Debug
Leveraging UVM and Discovery VIP for Better and Faster Verification
Author(s): Jason Chen, Navdeep Singh - Synopsys
Tutorial Videos

C2 Tutorial Session: IC Compiler ECO Flow For Minimum Physical Impact (MPI)
IC Compiler ECO Flows for Minimal Physical Impact
Author(s): Neil Moore - Synopsys
Tutorial

C3 User & Tutorial Session: Power Aware ATPG and Formality ECO
Speeding ECO Implementation and Verification with Formality Ultra
Author(s): Steve Lamb - Synopsys
Tutorial