SNUG Austin 2012 Proceedings |
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| | User Papers and Presentations | | FA1 User and Tutorial Session: Physical Synthesis, PrimeTime Performance, and Constraints Analysis | Advanced Design Partitioning with IC Compiler Leveraging Physical Synthesis (Technical Committee Award)
Author(s): Jack Randall (Advanced Micro Devices, Inc.) |
| | FA2 User and Tutorial Session: Cortex-A15 Best Practices and Structured Design | Efficient Reusable Structured Design Methodology
Author(s): Karthik Punukollu, Thomas Lin (Advanced Micro Devices, Inc.); Thomas Felske (Synopsys, Inc.) |
| Optimized Implementation of a Gigahertz+ ARM® Cortex™-A15 Processor using Tools included in the Galaxy Implementation Platform
Author(s): Brian Millar (Samsung); Chandu Challapalli (Synopsys, Inc.) |
| | FA3 User and Tutorial Session: Simulation Performance, Verification IP and X-Optimism | X-Optimism Elimination during RTL Verification
Author(s): Robert Booth (Freescale); Bruce S. Greene, Arturo Salz (Synopsys, Inc.) |
| SoC Simulation Performance: Bottlenecks and Remedies
Author(s): Patrick Hamilton, Richard Yin, Bobjee Nibhanupudi, Amol Bhinge (Freescale); Tareq Altakrouri (Synopsys, Inc.) |
| | FB1 User and Tutorial Session: Leakage Reduction and Processor Design | Solving for Leakage Power and Timing by Vt Swaps in PT-SI
Author(s): Chakradhar Tallury (Advanced Micro Devices, Inc.); Karthikeyan Karunanidhi (Open-Silicon) |
| | FB2 User and Tutorial Session: Cortex-A15 Best Practices and 20nm Design | High Performance Physical Design of a 28nm Quad-Core ARM Cortex-A15 with 4 MB L2 Cache (2nd Place - Best Paper)
Author(s): Jason Karka, Michael Robinson (Texas Instruments); Bill Sicaras (Synopsys, Inc.) |
| | FB3 User and Tutorial Session: Low power Verification, X-Propagation and Testbench Timing | Taming Testbench Timing: Time's Up for Clocking Block Confusion (1st Place - Best Paper)
Author(s): Jonathan Bromley, Kevin Johnston (Verilab) |
| Verifying a Low Power Design
Author(s): Asif Jafri (Verilab) |
| | FC1 User and Tutorial Session: Test Methodology | Multi-Scan Compression Support in an AMD Core
Author(s): Thomas Clouqueur, Martin Amodeo, Pankaj Sharma (AMD); Tim Yuan, Lori Schramm (Synopsys, Inc.) |
| Unified DFT Clock Architecture for Single Pass Timing Closure, Single Pass ATPG, Interface Characterization and Power
Author(s): Christopher Ryan, Kris Monsen, Scott Smith, Henry So - (Maxim Integrated Products) |
| | FC2 User and Tutorial Session: ICC Design Flows and Integrity/EM/IR Analysis | Clock Enable Timing Closure Methodology
Author(s): Harish Dangat, Senthilkumar Murugesan - (Samsung); Susheel Sharma - (Synopsys, Inc.) |
| Qualcomm DSP Semi-Custom Design Flow: Leveraging Place and Route Tools in Custom Circuit Design (3rd Place - Best Paper)
Author(s): Nadeem Eleyan, Patrick Szabo, Ken Lin, Paul Bassett, Masud Kamal (Qualcomm), Frank Glover (Synopsys, Inc.) |
| | FC3 User & Tutorial Session: Covergroups, Functional Coverage and Low Power Verification | 100% Functional Coverage-Driven Verification Flow
Author(s): Thinh Ngo, Sakar Jain (Freescale) |
| Using Covergroups and Covergroup Filters for Effective Functional Coverage
Author(s): Hillel Miller (Freescale) |
| | Tutorials | | FA1 User and Tutorial Session: Physical Synthesis, PrimeTime Performance, and Constraints Analysis | Galaxy Constraints Analyzer: Comparing Multiple SDC Constraints Files
Author(s): Robert Moore (Synopsys, Inc.) |
| Performance and Productivity Improvements in PrimeTime
Author(s): LaMark Chance (Synopsys, Inc.) |
| | FA2 User and Tutorial Session: Cortex-A15 Best Practices and Structured Design | Techniques for High Performance Cores using Synopsys Galaxy Platform—ARM® Cortex™-A15 Case Study
Author(s): Chandu Challapalli (Synopsys, Inc.) |
| | FA3 User and Tutorial Session: Simulation Performance, Verification IP and X-Optimism | Accelerated SoC Verification with Synopsys Discovery VIP for the ARM AMBA 4 ACE Protocol
Author(s): Chris Spear (Synopsys, Inc.) |
| | FB1 User and Tutorial Session: Leakage Reduction and Processor Design | Designing Programmable Hardware Accelerators: Gaining Flexibility Without Compromising Power, Area and Performance
Author(s): Drew Taussig (Synopsys, Inc.) |
| | FB2 User and Tutorial Session: Cortex-A15 Best Practices and 20nm Design | 20nm Double Pattern Technology in IC Compiler
Author(s): Zugang Li (Synopsys, Inc.) |
| | FB3 User and Tutorial Session: Low power Verification, X-Propagation and Testbench Timing | Getting X-Propogation Under Control
Author(s): Bruce Greene (Synopsys, Inc.) |
| | FC1 User and Tutorial Session: Test Methodology | Test Updates, Yield Improvement, and the Influence of Standards
Author(s): Adam Cron (Synopsys, Inc.) |
| | FC2 User and Tutorial Session: ICC Design Flows and Integrity/EM/IR Analysis | Accelerating PG Design Closure in IC Compiler with the Latest 2012.06 PrimeRail In-Design Rail Analysis
Author(s): Jason Binney (Synopsys, Inc.) |
| | FC3 User & Tutorial Session: Covergroups, Functional Coverage and Low Power Verification | Debug of Low Power Designs with Discovery Visualization Environment (DVE)
Author(s): Tom Powell (Synopsys, Inc.) |
| | Speech | | Lunch and Executive Address | Physics and Economics Are Driving Silicon Convergence
Author(s): Ty Garibay, VP of Engineering, Embedded Processing - Altera |
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