SNUG Austin 2011 Proceedings

2013201220112010
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Complete Proceedings


User Papers and Presentations
FA1 User - PrimeTime Flow, Analysis and Report Techiniques
An Accurate and Efficient Timing Signoff Flow for High-Performance Low-Power Microprocessors
Author(s): Yaping Zhan, David Newmark, Malisa Novakovic, Karthik Natarajan [Advanced Micro Devices, Inc.]
PaperPresentation

PrimeTime HTML - Reusable Web Reporting for PrimeTime
Author(s): Rathy Ung, Steven Woodward [On Semiconductor, Inc.]
PaperPresentation Tar.zip

Structural Clock Domain Crossing Analysis Using PrimeTime
Author(s): Shubhyant Chaturvedi [Advanced Micro Devices, Inc.]
PaperPresentation

FB1 User & Tutorial Session - DC Innovation and Multi-Tool Formal Verification
Multi-Tool Formal Verification
Author(s): Jonathan Wolfe [Samsung Electronics]
PaperPresentationSession Recording

FC1 User & Tutorial Session - DFTMAX and TetraMAX
DFTMAX and TetraMAX Adoption on AMD’s Bobcat Core (2nd Place - Best Paper)
Author(s): Shaishav Parikh, Vance Threatt and Andy Halliday [Advanced Micro Devices, Inc]; Glenn Boyer, Lori Schramm [Synopsys, Inc.]
PaperPresentation

Fault Grading via TetraMAX (1st Place - Best Paper)
Author(s): Anirudh Kadiyala, Vibhor Mittal, Atchyuth Gorti, Roystein Oliveira, Amit Pandey [Advanced Micro Devices, Inc.]
PaperPresentation

PA2 - User & Tutorial Session - High Performance Physical Design
Ultra High-Speed (5Ghz) Block Custom Physical Design Flow with ICC
Author(s): Prakash Jay, Suman Musunuru [Maxim Integrated Products, Inc.]
PaperPresentation

PB2 User - IC Compiler Implementation
Advanced Design Closure Techniques Using IC Compiler and Zroute on High Performance Designs at 32nm and Below (3rd Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Hongda Lu, Hyon Han, Yu-Ming Chiang [Advanced Micro Devices, Inc.]
PaperPresentation

Considerations and Challenges for Optimizing Leakage-Power at Sub-45nm
Author(s): Santhosh Pillai, Sarita Baswant [Samsung Semiconductors]; Susheel Sharma [Synopsys, Inc.]
PaperPresentation

PC2 User &Tutorial Session - IC Compiler Productivity & Design Complexity Challenges
Improving Productivity of Synthesis and P&R with Synopsys Physical Guidance (SPG) Technology
Author(s): Girish T P, Nishant Gaidhani, Lahari Samineni, George Jacob [AMD India Engineering Centre Pvt. Ltd.]
PaperPresentation

VA3 User & Tutorial Session - Coverage and Methodology
A Scalable SOC Functional Coverage Management Toolset
Author(s): Steven Farago, Farhan Rahman [Advanced Micro Devices, Inc.]
PaperPresentation

Random Instruction Stream Generator for a Many-Core uP
Author(s): Avery Topps, Mike Trocino [Coherent Logix, Inc.]
PaperPresentation

VB3 User - Compilation Performance and SVTB
Improving the Performance of Incremental Compilation inside a Complex SoC Verification Environment
Author(s): Patrick Hamilton, Amol Bhinge [Freescale Semiconductor]; Tareq Altakrouri [Synopsys, Inc.]
PaperPresentation

Object Oriented State Machines in SystemVerilog
Author(s): VJ Sananda [Advanced Micro Devices, Inc.]
PaperPresentation

VC3 User & Tutorial Session - Low Power and VCS Productivity
A Case For Optimizing Code Using VCS Profiling
Author(s): Steve Havlir [Advanced Micro Devices, Inc.]
PaperPresentation

Publication Only
Are We There Yet? A Verification Methodology for Functional Convergence
Author(s): Raymond Harlan [Coherent Logix]
Paper

Automated Flow for Generating CMOS Custom Memory Bit Map Information using ESPCV
Author(s): Nadeem Eleyan, Greg Seok, Hong Kim , Tung Pham, Rich McAuliffe [Qualcomm]
Paper (Coming Soon) Presentation (Coming Soon)

Power Intent Modeling and Verification Using ESP-CV In Low Power Design
Author(s): Tung Pham, Ken Lin, Paul Bassett [Qualcomm]
Paper

Tutorials
FB1 User & Tutorial Session - DC Innovation and Multi-Tool Formal Verification
Accelerating Design Cycle with DC Explorer
Author(s): Jenny Pencis [Synopsys, Inc.]
Tutorial

FC1 User & Tutorial Session - DFTMAX and TetraMAX
DFTMAX Compression, TetraMAX ATPG, STAR Memory System, and Yield Explorer: Accelerate Higher Quality, Lower Cost Test
Author(s): Tom Finklea [Synopsys, Inc.]
Tutorial

PA2 - User & Tutorial Session - High Performance Physical Design
Physical Datapath
Author(s): David Cantrell [Synopsys, Inc.]
Tutorial

PC2 User &Tutorial Session - IC Compiler Productivity & Design Complexity Challenges
Eliminating Late-Stage Manual Fixes With In-Design Physical Verification
Author(s): Dan Marolda [Synopsys, Inc.]
Tutorial

The Future of Complexity in Physical Design
Author(s): Henry Sheng [Synopsys, Inc.]

VA3 User & Tutorial Session - Coverage and Methodology
New Advancements in Methodology to Improve Verification Turnaround-Time
Author(s): Janick Bergeron [Synopsys, Inc.]
Tutorial

VC3 User & Tutorial Session - Low Power and VCS Productivity
New Technologies to Address Low Power Accuracy and Productivity
Author(s): Tom Powell [Synopsys, Inc.]
Tutorial

VCS Productivity Tools that Reduce Verification Cycle
Author(s): Dennis Strouphauer [Synopsys, Inc.]
Tutorial