SNUG Austin 2010 Proceedings
201220112010
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Complete Proceedings
User Papers and Presentations
TA1 Front-End Implementation
Reducing Flip-Flop Power in Hexagon Core Design and use of the Flop-Merging (2nd Place - Best Paper)
Author(s): Mohammed Shahid Imam, Martin Saint-Laurant [Qualcomm]
PaperPresentation
TA2 Physical Implementation
ICC Hierarchical Flow Enabling Parallel Implementation of the Top Level and the Child blocks
Author(s): Christian Cabel [Hewlett Packard Company], Chandu Challapalli [Synopsys, Inc.]
PaperPresentation
TA3 Digital Verification
Selection and Integration of a Signal Processing Package for a SystemVerilog/VMM Verification Environment
Author(s): Wes Kirk, Matt Spaethe [Motorola], Ron Shipp [Synopsys, Inc.]
PaperPresentation

Verification of the On-Chip network of a Many-Core Parallel Processor using SystemVerilog and VMM
Author(s): Bobby Purcell, Afzal Malik, Mike Trocino [Coherent Logix, Inc.]
PaperPresentation
TB1 Front-End Implementation
How to Reach High Performance with Tiempo Clockless Designs Using PrimeTime and IC Compiler
Author(s): Nicolas Leblond [Tiempo SAS]
PaperPresentation

Optimized ATPG Patterns: The Lowest Power For Your Buck
Author(s): Eric Pavao, Joe O'Neill, Michael Graham [Analog Devices, Inc.], Lori Schramm [Synopsys, Inc.]
PaperPresentation
TB2 Physical Implementation
Low Power Implementation using UPF in Synopsys's Lynx Design System for a USB 2.0 Hub
Author(s): Abid Jindani [SMSC]
PaperPresentation
TB3 Digital Verification
Verification of the CoreNet™ Fabric with SystemVerilog
Author(s): Robert Page, Sakar Jain [Freescale Semiconductor]
PaperPresentation
TC1 Front-End Implementation
Explore Your Design Visually Using PrimeTime & Gnuplot (Technical Committee Award Honorable Mention)
Author(s): John Paz, Sameer Shah and Colin MacDonald [Broadcom Corp.]
PaperPresentation

Timing and Power Analysis Issues in a Many-Core Processor Design Using ICC, PT, and PTPX
Author(s): Ken Faulkner [Coherent Logix Inc.]
PaperPresentation
TC2 Physical Implementation
Efficient Galaxy Flow Development with TCL
Author(s): Raymond Tang [Intrinsity, Inc.], Chandu Challapalli [Synopsys, Inc.]
PaperPresentation

Flop Clustering Algorithms to Reduce Clock Power (3rd Place - Best Paper)
Author(s): Hyon Han, Hongda Lu [Advanced Micro Devices], Tom Felske [Synopsys, Inc.]
PaperPresentation
TC3 Digital Verification
Database Schema for Very High Bandwidth Coverage Collection (1st Place - Best Paper)
Author(s): Mike Burns, James Roberts, Ray Voith [Oracle]
PaperPresentation
Publication Only
Improving Core Instruction Fetch Unit (IFU) Verification Through The Use of SystemVerilog Testbench
Author(s): Hiep Nguyen [MediaTek]
Paper

What's new? A simple template generator
Author(s): David C Black [XtremeEDA Corp.]
Paper
Tutorials
TA2 Physical Implementation
IC Compiler Feasibility Flow
Author(s): Imad Zaccak [Synopsys, Inc.]

IC Compiler: Planning & Implementation of Large Hierarchical Designs
Author(s): Imad Zaccak [Synopsys, Inc.]
TA3 Digital Verification
Low Power Verification
Author(s): David Lee [Synopsys, Inc.]
Tutorial
TB1 Front-End Implementation
Optimizing Compression and ATPG using Synopsys 2010.03
Author(s): Tom Finklea [Synopsys, Inc.]
Tutorial
TB2 Physical Implementation
Optimized Implementation Methodology for High Performance Low Power Process Cores at 40nm and Below
Author(s): Tom Felske [Synopsys, Inc.]
Tutorial
TB3 Digital Verification
Debugging Transactions
Author(s): Tareq Altakrouri [Synopsys, Inc.]
Tutorial

VCS 2010 Update
Author(s): Tom Powell [Synopsys, Inc.]
Tutorial
TC3 Digital Verification
Optimizing Coverage Turn-Around-Time w/ Unified Coverage Database
Author(s): Paul Graykowski [Synopsys, Inc.]
Tutorial


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