SNUG Canada Abstracts   

Monday, September 10, 2012
10:45 AM - 12:15 PM
MA1 User Session: Reuse and Methodology
Top-Down vs. Bottom-Up Verification Methodology for Complex ASICs
Paul Lungu, Zygmunt Pasturczyk (Ciena)
Next generation ASICs require special verification techniques and elaborate methodologies all within the constraints of the computing infrastructure and time. Given the size and the complexity of the devices under test, top level simulations alone will not do the job. This paper covers the simulation methodology used for two large ASICs requiring block level simulations. A top-down verification methodology was used for one of the ASICs while a larger version needed an expanded bottom-up approach using extended simulation capabilities. Some techniques and verification methods such as chaining of sub environments from block to top-level will be presented along with challenges and solutions found by the verification team. The paper will discuss a method of passing RAL mirror to the C models used as scoreboards in the environment. Also a method of generating stable clocks inside the "program" block is presented.

Developing a Re-Use Base Layer with UVM
Pierre Girodias (IDT)
Verification toolsets like UVM aim at facilitating the digital hardware verification process. They offer a coherent and consistent framework that captures the best practices in the industry in a library of classes, and defines application guidelines based on OOP concepts. One common recommendation is that adopters of these “methodologies” should develop a base layer. A base layer consists of a set of generic classes that extend the classes of the original toolset. It provides a convenient location to develop and share the processes that are relevant to an organization for re-use across different projects. However, creating a base layer requires a solid understanding of inheritance, polymorphism and, of course, UVM. Our paper identifies typical problems: living without multiple-inheritance and foraging through class templates. We detail possible solutions while also illustrating, through the creation of highly re-usable agents, the advantages of using a base layer.

A Mechanism for Hierarchical Reuse of Interface Bindings
Thomas Zboril (Qualcomm Atheros)
A method to instantiate SV interfaces, connect them to the DUT and wrap the virtual interfaces for use in the test environment will be presented. This method allows the reuse of all the code when the DUT becomes an instance in a larger subsystem or chip. The method involves three key mechanisms:
  • Hierarchical virtual interface wrappers (standard practice)
  • Hierarchical instantiation of SV interfaces (new)
  • Automatic management of hierarchical references via SV macros (new)


MA2 Tutorial & User Session: Custom Designer Accelerators and Revision Control
Using Custom Designer Accelerators to Speed-up your Design Cycle
Nic Regis (Synopsys, Inc.)
The increased complexity of today’s analog designs is forcing analog designers to look for new approaches at solving their implementation and verification challenges.  This tutorial will demonstrate a set of features in Synopsys Custom Designer to speed-up analog design implementation and verification.  Target audience: Analog designers, analog mixed signal engineers and managers.

Integrating SVN Revision Control Software with Synopsys Custom Designer
James Cherry (Kapik Integration)
We discuss how to use the Tcl API in Synopsys Custom Designer to integrate revision control of schematics, layouts, and other cells using Subversion (SVN), an open source revision control software package. We also walk through our implementation: menu entries, dialog boxes, and the like.


MA3 Tutorial Session: Signoff Driven Design Closure, and Route Correlation
ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing
Pervinder Trehan (Synopsys, Inc.)
PrimeTime’s 2012.06 release extends the production-proven ECO technology from earlier releases to multiple new areas of design rule constraint (DRC) fixing. Together, PrimeTime ECO enables you to perform ECO fixing for timing and DRC across multiple scenarios in parallel using CPU resources efficiently from your compute environment. New enhancements in DRC fixing include trade-offs for timing costs and a flexible approach to utilizing compute resources for multi-scenario fixing. This tutorial is for designers responsible for timing convergence and signoff and will show how users are effectively using PrimeTime’s ECO solution with the latest ICC flows.

Intelligent and Automated Layer-Aware Pre-Route Optimization for Improved Post-Route Correlation for Advanced Technology Nodes
Eric Antognelli (Synopsys, Inc.)
At 28nm and below, wire resistance varies significantly across routing layers. Layer average pre-route parasitic estimation is too pessimistic for long nets which lead to over buffering and poorer post-route correlation. In this tutorial, we shall describe the use of net patterns and layer-awareness throughout the implementation flow for more accurate pre-route parasitic estimation that avoids over buffering and results in tighter post-route correlation.


MA4 User and Tutorial Session: Test Coverage and Design Exploration
I Upped My Coverage, Up Yours!
Martin Salomon (STMicroelectronics, Inc.)
A methodology is explored, in which certain flops in the scan path are controlled using a separate shift_enable signal, conditioned with other signals, which would allow user logic, in the form of an exclusive-or tree, to be inserted in between the scan path, enabling users to obtain extra coverage should it be required. This is an extension of the paper “Hijacking Flops for Fun and Profit” [Salomon, STMicroelectronics], in which the D inputs of flops are used for a similar purpose.

Synopsys DC Explorer and 2012.06 Design Compiler Highlights
Bob Wiegand (Synopsys Inc.)
We’ll show how DC Explorer provides early RTL exploration—before the RTL and constraints are complete—so designers can quickly improve the design data and create a better starting point for synthesis. We’ll also discuss how DC Explorer works alongside other products in the Synopsys Galaxy™ Implementation Platform to enable early design planning, physical feasibility analysis, and constraint analysis. Then we’ll highlight new features in the Design Compiler® 2012.06 release and how it boosts performance and productivity with faster timing in Synopsys Physical Guidance. Target audience: Designers and managers with responsibilities or interests in synthesis and design methodology.


Monday, September 10, 2012
1:15 PM - 2:45 PM
MB1 Tutorial & User Session: DVE and Low Power Verification
Live Demo: Debugging UVM testbench and Constraint with DVE
Jason Chen (Synopsys, Inc.)
With the adoption of advanced verification methodologies such as UVM, additional protocol complexities and complex testbench constraints, fast and efficient debugging becomes increasingly important. Join us for this live demonstration showing some techniques to decrease your debug cycle using the latest VCS debug capabilities. This demonstration will include new capabilities to simplify debugging of your UVM testbench, track dynamic data,  interactively debug constraints and perform what-if analysis on your SystemVerilog testbench.
Target audience: Verification engineers and design managers.

Insight Into Power Gating Verification
Ashwini Chandrashekhara Holla (Advanced Micro Devices)
IC manufacturing technology has seen tremendous progress in miniaturisation resulting in very complex designs and thereby more complex problems to solve, one of the most important being power. In submicron technologies that are being employed today, static power dissipation is becoming as significant as dynamic power dissipation resulting in a need for power gateable designs. Power gating, being a relatively newer concern and hence not a mature subject matter, presents many new challenges in verification. In this paper I would like to discuss the history of power gating, methodology of power gating verification, challenges involved and the role of EDA tool in the entire process.


MB2 Tutorial Session: Preventing Electromigration and ERC/ESD
An Automated Method for Avoiding Electromigration Failures During Layout Creation
Faisal Saleh (Synopsys, Inc.)
As we move to smaller nodes electromigration issues are starting to occur not just in power rails but on signal nets.  In some cases these issues are caught after layout is complete, potentially causing deadlines to slip and significant layout rework.  This presentation covers a flow used to prevent electomigration issues during layout creation. Target audience: Analog designers, analog mixed signal engineers and managers.

IP Validator
Glen Hertz (Synopsys, Inc.)
When issues arise when integrating 3rd party IP it is often difficult to pin-point the source of the problem.  This tutorial covers features to analyze 3rd party and internal IP for ERC and ESD violations.  We will demonstrate checks for missing ESD protection, power down induced leakage, missing level shifters, high impedance nodes, and how to create custom checks by utilizing CustomSim-CircuitCheck technology.
Target audience: Analog designers, analog mixed signal engineers and managers.


MB3 Tutorial Session: Top Level Closure and Multi-IO Ring Design
Faster Top Level Closure With Transparent Interface Optimization (TIO)
Jim Lehman (Synopsys, Inc.)
Transparent Interface Optimization (TIO) in IC Compiler is a new capability that addresses the challenges of gigascale design and enables faster top-level closure. This tutorial will provide designers technical information on TIO, its usage, current capabilities and roadmap.
Target audience: Design and CAD engineers and managers responsible for physical implementation and verification.

Creating Multi-IO Ring Die Using IC Compiler
Sufyan Khan (Synopsys, Inc.)
As technology nodes continue to shrink, often die size is limited by the size required to form a single, perimeter ring of IO drivers. To minimize die size, most design teams faced with pad limited die sizes are turning to multi-IO ring layouts. This tutorial walks through how to create multiple IO rings on a die, and how to populate the rings with both general purpose IO drivers and IO macros. The multi-IO ring layouts can be used for both wire bond and flip chip packaging. The tutorial is targeted for physical design engineers and managers.


MB4 Tutorial Session: ECO Timing Closure & PrimeTime/PrimeTime SI
ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing
Pervinder Trehan (Synopsys, Inc.)
PrimeTime extends the production-proven ECO technology from earlier releases to multiple new areas of design rule constraint (DRC) fixing. Together, PrimeTime ECO enables you to perform ECO fixing for timing and DRC across multiple scenarios in parallel using CPU resources efficiently from your compute environment. New enhancements in DRC fixing include trade-offs for timing costs and a flexible approach to utilizing compute resources for multi-scenario fixing. This tutorial is for designers responsible for timing convergence and signoff and will show how users are effectively using PrimeTime’s ECO solution with the latest ICC flows.
Target Audience: Designers and managers with responsibility or interest in timing closure.

PrimeTime/PrimeTime-SI  2011/2012 Special Topics and Methodology
Paul Lamers (Synopsys, Inc.)
Over the last 2 years Primetime has continued to improve usability, performance, and capacity.  This presentation will review a selection of changes you might have missed for methodologies and features; report_timing, muli-core, crosstalk analysis, etc.
Target Audience: Designers and managers with responsibilities or interests in STA analysis and methodology.


Monday, September 10, 2012
3:10 PM - 4:40 PM
MC1 User Session: Stimulus Generation, Constraint Random and Error Injection
Verification of a Custom RISC Processor
Andrew Elms (Huawei Canada);
VMM provides a proven verification solution that addresses many verification challenges. This paper presents the successful application of VMM to the verification of a custom RISC processer. The challenges in verifying a programmable design and solutions that can be broadly applied are presented. Three topics explored in detail are the use of Verification Planner, constrained random generation of instructions and coverage closure. The importance of the Verification Plan as the foundation for the verification effort is investigated. A surprising conclusion from the plan is that generating production software constructs, such as while-loops, is not necessary to verify this design.
Enhancements to the VMM generators are also explored. By default VMM data generation is independent of the current design state, such as register values and outstanding requests. RAL and generator callbacks are used to address this.
Finally, our experience with coverage closure and suggestions for future investigation are presented.

A Perspective on Soft and Default Constraints
Karim Khordoc (Cisco Systems); Jason Chen (Synopsys, Inc.);
Soft constraints are defined in the upcoming SystemVerilog LRM update. Their semantics require a mechanism in the constraint solver to automatically disregard them when they are overridden by "subsequent", more specialized constraints. VCS supports another constraint overriding mechanism called default constraints, outside of the SystemVerilog LRM. Through examples, this paper shows how default and soft constraints work and how they can be used in practice in addressing typical verification situations and in expressing appropriate solution sub-spaces, e.g., when targeting corner cases. Using these examples, the paper compares these two constraint paradigms and makes recommendations on how to use them effectively.

UVM Sequence Item Based Error Injection
Jeffrey Montesano, Mark Litterick (Verilab)
The proper testing of most digital designs requires that error conditions be stimulated to verify that the design either handles them in the expected fashion, or ignores them, but in all cases recovers gracefully. A self-checking constrained-random envi-ronment can be put to the test when injecting errors, because unlike the device-under-test (DUT) which can potentially ignore an error, the testbench is required to recognize it, potentially classify it, and determine an appropriate response from the design. In this paper we will present an error injection strategy using UVM that meets all of these requirements. The strategy encompasses both active and reactive components, with code examples provided to illustrate the implementation details.


MC2 Tutorial Session: Advanced Interactive Debugging Utilities in ICV
Advanced Interactive Debugging Utilities in ICV
Tim Guttormson (Synopsys, Inc.)
Debugging physical design errors like shorts and complex design rule violations are time consuming endeavours.   Synopsys' IC Validator is at the forefront of new ideas and capabilities helping keep designer productivity in step with increasingly complex designs.   This tutorial will cover the latest in both production and alpha level features for debugging complex designs on advanced process nodes.
Target audience: Analog designers, analog mixed signal engineers and managers.


MC3 Tutorial Session: High Performance Cores and 20nm Design Success
Techniques for High Performance Cores using Synopsys Galaxy Platform-ARM® Cortex-A15 Case Study
Daniel Biset (Synopsys, Inc.)
Learn how to predictably achieve high performance while minimizing power. We will present an optimized implementation methodology for an ARM Cortex™-A15 processor core based on Synopsys’ Galaxy™ Implementation platform. This session will highlight the latest technologies/techniques in Design Compiler and IC Compiler used to achieve challenging performance/power targets. These include physical guidance, delay performance vs. area tradeoffs, leakage optimization, innovative methods to reduce slack across register stages during final timing closure, and more. We will examine benefit/cost tradeoffs of each technique; performance/ease of convergence and impact on schedule/turnaround time. We will also share results obtained using this combination of optimized methodology, tools and physical IP.

IC Compiler: Achieving Design Success at 20nm
Sufyan Khan (Synopsys, Inc.)
Advanced technology nodes present a whole new set of design challenges in achieving Timing and Place and Route closure. This tutorial discusses the 20nm design challenges such as advanced technology design rules (DRC), double pattern technology (DPT), optimal standard cell library layout and demonstrate how IC Compiler will help you achieve DPT compliant layout with In-Design Signoff Analysis and Repair capability.
Target audience: Physical designers and managers.


MC4 User & Tutorial Session: Constraint Analysis
Reducing STA Constraints Churn Using GCA
Brian Silveira (Huawei Canada)
This paper discusses a case study of Galaxy Constraints Analyzer (GCA) on an ASIC project using Primetime for STA. The paper will focus on the ease of use and sharing of scripts between GCA and PrimeTime, more then just the constraints. Specific examples will be presented to show how GCA uncovered clocking errors and improved the quality of the constraints months before handing off the constraints to the PD/backend ASIC vendor; the vendor was responsible for all ASIC PD and backend work. Additional examples will depict how the debugging features helped in quickly resolving constraints issues, GCA errors and GCA warnings. GCA was integral to review the constraints with our vendor, and this paper will discuss how waivers were shared between the vendor and ourselves to help close constraints issues.

Minimizing Risk in Multi-Clock Designs with GCA
Mark DiGiovanni (Synopsys Inc.)
Today’s multi-clock designs make constraint development more difficult, and increase the risk of clock setup errors impacting your schedule. In this tutorial we will show how Galaxy Constraint Analyzer (GCA) can be used to confirm you have complete and correct constraints, and to identify structural problems in your design that impact the integrity of your clock network. During the tutorial we will explore the host of debug options available in GCA that allow you to better understand the issues identified and guide you to solutions. We’ll also look at how GCA interfaces with DC Explorer to enable constraint analysis at the earliest stages of your design flow.
Target audience: Designers and managers with responsibility or interests in constraint development and analysis in implementation flows.


Disciplined Design Documentation Dextrously Done with UML
Bryan Morris (Verilab)