| Time | Description |
| 8:30-9:30 | Registration & Breakfast |
| 9:00-9:15 | Welcome
Zachi Feldman, Broadcom, SNUG Israel User Chair |
| 9:15-10:45 | Keynote
Dr. Antun Domic
Senior Vice President and General Manager, Implementation Group, Synopsys | Industry Keynote
Lance Howarth
Executive Vice President of Marketing, ARM |
|
| 10:45-11:15 | Break |
| | Verification Track
Room A10 | FPGA Prototyping and System Track
Room A4 | Implementation
A
Room A3 | Implementation
B
Room A2 | AMS & IT Track
Room A5 | IP Track
Room A1
|
| 11:15-12:45 | A1 User Papers and Tutorial: xProp, Native Low- Power, Soft Constraints
Improved X-Propagation using the xProp Technology
Rafi Spigelman, Intel
Power Aware Verification for CPU Designs: Challenges and Solutions
Adriana Wolffberg, Anees Sutarwala, Intel
Introduction to Soft Constraints in SystemVerilog
Alex Shot, Jason Chen, Synopsys | A2 Tutorial:
Considerations in Using FPGAs as System Elements
Andrew Dauman,
Synopsys | A3 Tutorial and User Paper: Design Compiler 2012.06 Updates and Multibit FF Inferring
Galaxy RTL: Design Compiler Family Update
Eyal Odiz, Gal Hason, Synopsys
Inferring Multi (dual) Bit FFs in Synopsys RTL2GDSII Flow
Oren Unger, Raz Dagan, Omer Niv, CSR (Zoran Microelectronics) | A4 Tutorial and Vision: ICC 2012.06 Updates and 2.5D IC Vision
ICC 2012.06 Updates
Zvi Webb, Synopsys
Vision Session: Advanced Design Integration – 2.5DIC and 3DIC
A Silicon Interposer-Based 2.5D-IC Design Flow - Going 3D by Evolution Rather than by Revolution
Marco Casale-Rossi, Synopsys | A5 FastSPICE – Overview and User Experience:
FastSPICE Solutions Overview
Dr. Isaac Zafrany,
Synopsys
Methods for Running Fast SPICE (XA) for SPICE level Accuracy on Advanced Analog Circuits
Yoav Levi, Zelig Wayner; Intel
Utilizing SystemVerilog for Mixed Signal Validation
Gabi Glasser; Intel | A6 Tutorial:
Best Practices for Implementing Memories and Libraries to Deliver Superior PPA and Embedded Test & Repair
Zaka Bhatti,
Synopsys |
| 12:45-1:30 | Lunch |
| 1:30-3:00 | B1 Tutorial:
Leveraging Synopsys’ Next-Generation SystemVerilog VIP
Chris Thompson,
Synopsys, Inc | B2 Tutorial: FPGA Best Practices and Hybrid Prototyping
FPGA-Based Prototyping with Certify & Identify
Yair Dahan, Synopsys
Hybrid Prototyping - Connecting Virtual and FPGA Prototypes
for Earlier HW/SW Development.
Ohad Amrami, Synopsys; Yair Dahan, Synopsys | B3 Tutorial & Panel: Optimized Implementation for High Performance Cores
Techniques for High Performance Cores Using Synopsys Galaxy Platform-ARM®Cortex™-A15 Case Study
Dror Rishin, Synopsys, Inc.
Ask the Experts Panel: Best Practices for High Performance Processor Core Implementation | B4 User Papers: Load Density Driven Power Grid; Verification of Layout Integration Flow; OCC Controller
Load Density Driven Power Grid Design
Farah Jubran, Mellanox Technologies
Verification of Layout Integration Flow
Yulia Goldshtein, Intel
On-Chip-Clock controller (OCC): An Alternative Approach
Jalal Abu Teir, Joram Peer, Nuvoton | B5 Tutorial:
How to Get the Most from Your Circuit Simulation
Dr. Isaac Zafrany;
Synopsys Inc. | B6 User Paper and Tutorial: Connectivity IPs
Third Party Connectivity IP – Expectations and Experience
Roman Mostinski, Freescale
Designing to the New PCI Express 3.0 Equalization Requirements
Rita Horner
Synopsys, Inc. |
| 3:00-3:20 | Break |
| 3:20-4:50 | C1 User Papers: Verification Abstraction, Reusable Testbench, Design Patterns
The End of Verification?
Kobi Pines,
Marvell
Truly Reusable Testbench to RTL Connection for SystemVerilog
Arik Shmayovitsh,
Sigma Design
Design Patterns in Verification
Guy Levenbroun, Qualcomm | C2 Tutorials:
Software Development for ARM big.LITTLE and Procesor Design
Robert Kaye - ARM ; Achim Nohl -Synopsys
Application-Specific Processor Design
Achim Nohl,
Synopsys | C3 Tutorial: IC Compiler Custom Co-Design
Design Closure | C4 User & Tutorial Session: Design Planning; Top-level Closure (TIO); Flip-Chip
Hippo Lake: A Case Study of Automated Design Planning in High Speed Designs
Justin Barber, Victoria Kolesov, Atul Walimbe, Michael McCoy
Intel
Faster Top-Level Closure With Transparent Interface Optimization (TIO)
Sharon Avital,
Synopsys
Flip-chip Package Support Solution Based on ICC 2012.06 Release
Moshe Ashkenazi,
Synopsys | C5 Tutorials: IT for EDA
Leveraging Adaptive Resource Optimization with Lynx
Glenn Newell,
Synopsys
Management of High-Performance Compute Resources - Understanding the Impact of NFS Overhead
Glenn Newell,
Synopsys | C6 Tutorials: Enhancing DesignWare ARC Processor Performance; Complete Audio IP Subsystem for Your SoC
Enhancing DesignWare ARC Processor Performance Using Custom Extension Instructions
Steve Tateosian, Synopsys
Create a Complete Audio IP Subsystem for Your SoC
Shlomi Dan,
Synopsys |
| 4:50-5:00 | Best Paper Award and Prize Drawing |