Conference at a Glance  

SNUG India | June 13-14, 2012 

ITC Gardenia, Bengaluru*
No.1, Residency Road
Bengaluru (Bangalore) 560025
Karnataka, India
* New Venue

Wednesday, 13 June, 2012
Thursday, 14 June, 2012

Wednesday, 13 June, 2012


Registration and Breakfast
Welcome and Keynote
Manjunath D Haritsa, Director, Applications Consulting, Synopsys India
Deirdre Hanford, Sr. Vice President, Global Technical Services, Synopsys, Inc.

IC Verification

IC Design: Signoff

IC Design: Test & FPGA

10:30-12:15TA1 Tutorial & User Session
Topics include: Verification Convergence with AMBA ACE VIP; X-Prop; and VMM VIP
TB1 Tutorial & User Sessions
Topics include Parasitic Extraction for Emerging Technologies; Simultaneous Multiple Input Transition Effect on Complex Gates; and Early Power Estimation using Primetime-PX.
TC1 User Sessions (Test)
Users will discuss topics including: Reducing Scan ATPG Overhead; Improving Quality of Memory Interface Tests; TCAM BIST Methodology; and Reducing Peak Power Consumption During Scan Shift
13:15-13:30TA2 User Session
Reset Logic Verification; Integration of SystemC OSCI TLM 2.0 Models to OVM; and Runtime Optimization
13:30-14:45TB2 User Session
User Papers on Improving Constraints Quality; Vector Based Reliability Signoff for IOs; and Dynamic IR Drop Analysis
TC2 Tutorial and User Session (FPGA)
Speeding up FPGA Implementation & Debug and FPGA Prototype of Communications Subsystem for IP validation
15:00-15:15TA3 User Session
Users will present papers discussing a Methodology for Dual NIC SoCs and SoCs with Embedded Processors
TC3 Tutorial & User Sessions (FPGA)
Managing the challenges in large FPGA designs; User paper on pre-silicon verification & validation and novel approach for gated clock conversion in multi FPGA platform
15:15-16:00TB3 Tutorial & User Session
Update on STA performance Improvements and User Papers on Power Computation & IR Drop Methodology for DDR PHY.
Designer Community Expo
Primetime SIG (Hyperscale)
(Special Invitation Required)
Designer Community Expo

Thursday, 14 June, 2012
Registration and Breakfast
Welcome and Customer Keynote
Dr. Aloknath De, Chief Technology Officer, Samsung India Software Operation Pvt. Ltd

IC Design:

IC Design: Low Power

Custom Design and AMS Verification

Systems & IP

10:15-12:15FA1 Vision & User Session
Synopsys Vision Session: Designing 100 Billion Transistor Chips; User papers on productivity improvements and faster design closure
FB1 User Sessions and Vision
User papers on UPF-aware verification and implementation flow; Vision Session: Low Power Design: How Long Until We Hit the Wall?
FC1 Vision & User Session
Synopsys Vision Session: Semiconductor Trends and Challenges for the Future; User papers on mixed signal designs using XA-VCS; Custom Explorer waveform comparison
FD1 Tutorial & User Sessions
Topics Include: Developing Software for ARM big.LITTLE Based Designs Running Android; User papers on Co-sim and System Performance Analysis
13:15-15:15FA2 User Sessions
User papers discuss Auto DRC Repair Flow and A Novel Implementation Approach for SoC Pin Timing Closure
FB2 User Session
User papers on Low- Power Design Challenges
FC2 Tutorial & User Session
Tutorial: How to Get the Most from Your Circuit Simulation; User paper on CustomSim XA for IO verification and reliability check
FD2 Tutorial & User Session
Tutorial on USB3.0 and Best Practices for Implementing Memories and Libraries; User paper on a core tool to integrate multiple IPS
15:30-17:00FA3 Panel and User Session
User papers and panel discussion on high performance cores
FC3 User Session
User papers on net-matching constraints, Hybrid Full Chip SPICE Simulation, Verification using CustomExplorer Ultra and ESP-CV
FD3 Tutorial Sessions
Best Practices for Implementing Memories and Libraries to Deliver Superior PPA ; Early SoC Architecture/Performance Modeling using SystemC/TLM 2.0
Best Paper Awards