|Wednesday, June 12, 2013|
9:00 AM - 10:15 AM
|Keynote Address |
|Massive Innovation and Collaboration into the "GigaScale" Age!|
Aart de Geus, Chairman and co-CEO - Synopsys, Inc.
The semiconductor industry is on the bridge to a new world of complexity empowered by smaller dimensions, new transistor types, enormous IP reuse, and a focus on the great potential of electronic systems. In other words, the GigaScale Age is upon us!
In addition, our customers are facing uncertain markets where merely making a better version of their last product is not sufficient. To survive and thrive in new and unknown markets, designers and their ecosystem partners are accelerating both their innovation and their collaboration with key partners. They expect the same from their EDA, IP and services partners.
In his presentation, Aart will give an overview of the enormous amount of recent innovation and collaboration happening at Synopsys as we enable "Moore’s Law plus, plus" for yet another decade!
|Wednesday, June 12, 2013|
10:30 AM - 12:15 PM
|WA1: Synopsys User and Tutorial Sessions|
|WA1.1 Tutorial: Zebu Overview, Easier HDL Cosim, Productivity Techniques |
In this tutorial you will receive an overview of the the Zebu platform and an introduction to the verification and validation use cases afforded by this platform. You will learn how to enable HDL Cosim to improve simulation performance and the nuances of getting the best results. Additional techniques to swap between simulation and emulation and restoring saved simulations in emulation will be expounded upon
|WA1.2 User Paper: Zebu Transactors for Verification & Validation|
Karthikeyan Rajamanickam - Texas Instruments
Our main focus is on pre-silicon verification and validation capabilities adopted using Zebu Transactors at different levels, bridging the gap between simulation and silicon. Transactors also aid in areas on porting the ASIC RTL to pre-silicon with minimum modifications. Given its non-intrusive instrumentation capabilities, it helps in collection of statistical data for profiling when system runs at a reasonable speed when simulation is an impossible task. ZRM provides easier access for data pre-processing adding value to architecture evaluation. The session will also cover a use model for functional verification to analyze complex sequence of events and enable triggers/signal events. On to verification automation support, we mimic the FPGA used along with silicon to provide test support and additional functionalities to the RTB using a transactor, which works seamlessly compared to hardware connectors on silicon-based test set-up.
|WA1.3 User Paper: Innovative Approach to Overcome Limitations of Netlist Simulation|
Prodip Kundu, Pankaj Singh, Narendran Kumaragurunathan, Meera Mohan - AMD India Pvt. Ltd
One of the biggest challenges in running gate-level simulations is to quickly find or debug the source of the failing node. This paper elaborates on a proposed automated flow using Verdi APIs to enhance the debug capability during the gate-level simulation debug to get to the root cause of the failure. This automated signature assignment-debug process helps ensure the team is focused on solving critical mis-compares and thus meeting the schedule. In this paper we will share this flow, based on several bugs which we found during the netlist simulation of a real design.
|WB1: Synopsys User and Tutorial Sessions|
|WB1.1 User Paper: Addressing Signoff Timing Quality and Cycle Time Challenges in High Performance Processor Designs|
This paper showcases the flows and methodologies developed to address critical challenges and improve the cycle time/efficiency of timing closure in High Performance Processor designs. We enabled over-night flat analysis for large hierarchies of the design using the tools runtime/capacity, greatly reducing the scope of hierarchical model generation/validation/usage. Along with the integrated noise analysis, this brought a significant improvement in overall cycle time. From a feature standpoint, a MIS modeling approach for hold closure was implemented. We use a custom rule-based ERC/Timing quality checker, to meet stringent quality and timing requirements for CPU designs.
This paper will discuss native ECO fixing and what-if capabilities which enabled a push-button setup/hold/drc fixing solution in the closing stages of timing closure as compared to more effort intensive manual/custom fixing solutions. We are also evaluating an improved hierarchical solution to replace traditional block modeling for reducing cycle time and use AOCVM for pessimism reduction on high-speed paths.
|WB1.2 User Paper: Novel Approach to do Multi Voltage Signoff using SMVA|
Ish Chadha - NVIDIA
Low power brings new challenges in form of MV domain & dynamic voltage and frequency scaling (DVFS). Traditional STA for handling single power domain linked signoff vs. covering all MV/DVFS/use-cases brings its own challenges. To cover challenges signoff flow based on link per instance and derate were developed to cover MV/DVFS/use-cases scenarios. However with an increase in the number of voltage domains and use cases the number of possible combinations for signoff has increased dramatically. In-house MV signoff flows can’t handle such large of scenarios without compromising on accuracy or incurring a large runtime penalty. Hence alternate approaches that could scale with future needs had to evaluated/developed. In this paper we will go through an SMVA based MV sign off flow that has been deployed on a recent complex mobile chip. The paper will discuss the challenges and advantages offered by SMVA. It will also discuss some of limitation, enhancements/recommendations for future.
|WB 1.3 Tutorial: PrimeTime - Key Technologies and Release Updates|
This tutorial will focus on some of the key technologies that help improve productivity and reduce turn around time in multi-million gate designs today. Topics covered include:
- Achieving faster timing signoff for multi-voltage designs, while avoiding the risk associated with margining-based approaches using the Simultaneous Multi Voltage Analysis (SMVA) feature of PrimeTime.
- How PrimeTime-GCA helps reduce the cycle time in validation of constraints and the new native feature in PrimeTime that allows constraints checking.
- Latest release updates and productivity improvements in PrimeTime.
|WC1: Synopsys User and Tutorial Sessions|
|WC1.1 Tutorial: Laker Custom Layout System - "An Advanced Process Node Custom Layout Tutorial"|
In this technology session you will learn about the new layout challenges introduced by 20nm and below process technology. You’ll also see the advanced features in the Laker Custom Layout Solution that help with these issues. Laker is extremely fast and has unique automation features that are ideal solutions for those seeking to improve layout productivity.
Technologies that will be covered in this tutorial include Laker’s rule-based layout, schematic-driven layout, and pattern-based multi-device layout features — which have been all fully updated for process nodes at 20 nanometers and below.
|WC1.2 User Paper: FineSim for Complex Mixed-Signal SoC Verification|
Anmol Mahajan, Amit Kumar Singh, Karthik Sundararaj - Analog Devices, India, Vivek Sharma - Synopsys
With ever increasing size and complexity of mixed-signal SoC (System on Chip) designs and aggressive time-to-market constraints, there is a need to uncover any potential functional and performance issues in silicon much before tape out.
In this paper we will discuss the application of FineSim and its value addition to mixed-signal verification and sign-off for two large mixed signal SoCs. The methodology used and challenges faced in deployment of FineSim towards the same will be covered. We will present details on critical power-up issues in one of the designs uncovered by the full chip simulation using FineSim, eventually avoiding a potential silicon re-spin. We will present correlation for power numbers obtained in simulations with silicon measurements for the other design. We will also discuss future scope applications of FineSim for post layout effect simulation, dynamic voltage drop and electro-migration analysis at block and chip level.
|WC1.3 User Paper: Custom Routing Flow Enablement for Advanced Nodes|
The increasing complexity of manufacturing rules has made the often hand crafted custom digital and analog layout process very time intensive. At advanced nodes, electrical and manufacturing concerns have introduced specific and inconsistent rules. This demands a great degree of automation in custom routing to improve the layout turnaround time. Satisfying the analog designers requires a host of special requirements such as support for differential pair, buses, RC matching, and shielding in addition to a standard gridless routing.
This paper focusses on the rolling out of a custom routing flow using the Titan Shape Based Router (SBR) for advanced nodes. The core router with open access database support has been configured with advanced DRC rules to support the complete set of manufacturing rules. Constraint-driven routing flow with support to bus routing, differential pair, tandem/coaxial shielding, multi-layer length matching and RC matching has been enabled.
|WD1: Synopsys User and Tutorial Sessions|
|WD1.1 User Paper: Increase ATPG Throughput While Reducing Care Bits: Optimizing Transition Fault Patterns|
Mudasir Kawoosa, Rajesh Mittal, Prakash Narayanan - Texas Instruments, Surya Samavedam - NVIDIA
Test time reduction for application of scan patterns using an ATPG tool can be achieved in several ways. Examples include using scan compression to increase the number of internal STUMPS while reducing the STUMPS length, increasing the internal shift frequency, reducing the idle time between the shift and capture phases, etc. All of these techniques are well understood and have been exploited in design, DFT and ATPG tools. In this paper we propose a new approach towards test time reduction with scan patterns. This is based on reducing care bits that need to be constrained during transition fault pattern generation so as to reduce the effect of constraints bits and thereby achieve more coverage and reduced pattern count.
|WD1.2 User Paper: Effective ATPG with Hierarchical DFT Methodology for SoC|
Seema Shareef, Soham Roy, Ashwini Shankar - Wipro Technologies
With growing design complexities, the general way of flat DFT methodology is not practical any more. Flat designs are prone to larger simulation run times and pose difficulty during diagnosis and debug. In this paper, a hierarchical approach to DFT is presented to tackle the problems encountered when incorporating DFT to SOC designs. We propose a hierarchical DFT methodology in conjunction with reduced pin count test. We show that it is feasible to achieve better ATPG results with a comprehensive hierarchical DFT for System-on-chip devices.
|WD1.3 User Paper: Sharing Scan-Ins For Similar Cores |
Deepak Agrawal, Daryl Pereira, Sanjay Shinde, Aanand Venkatachalam - LSI India
As the technology is shrinking the SOCs are growing in density and gate count. This creates challenges regarding the testability and more importantly the test cost. Almost all big SOCs have physical hierarchies for implementation. Also many of today’s SOCs have multiple instances of a few modules. This gives an opportunity to optimize test cost. This paper demonstrates how we handled the scan implementation for our design. We also addressed the complexity related to multiple levels of physical hierarchy as the block is instantiated inside another physical hierarchy. We will discuss how we used the shared scan-in’s feature of DFT-MAX for the block instantiated multiple times. Finally we will share how this approach helped reduce the test data volume/ test pin requirements and still retain full observability on the scan output.
|WD1.4: New, Innovative Test Technology to Reduce the Cost of Quality|
Rohit Kapur - Synopsys
About a dozen years ago, one DFT methodology—scan compression—addressed the fundamental need to lower test costs while maintaining high quality and high productivity. Although DFT methodologies have since kept pace with design and test requirements, in a few years SoCs likely will be an order of magnitude more complex than today’s designs and contain hundreds, if not thousands, of cores. This session will focus on exciting advancements in DFT to meet the test cost, quality, and design closure requirements of the next generation of SoCs.
|Wednesday, June 12, 2013|
1:15 PM - 2:45 PM
|WA2: Synopsys User Session|
|WA2.1 User Paper: X-Propagation - Improving the Methodology in Uncovering X-optimism Issues|
Ashish Gogia - Cisco Systems India, Shekhar Basavanna, Vasudev Srinivasan - Synopsys
The gate level simulations (GLS) play a critical part in the verification cycle to catch the X-optimism issues missed during RTL simulations, though it could still leave some functional bugs due to its inherently non-exhaustive nature. This paper talks about VCS’s new technology X-propagation (X-prop) and our experience with it and how it helped in mitigating some of these concerns and improving the overall process. The paper talks in detail about the two modes of Xprop feature – T-merge and X-merge, and their usage in uncovering potential design bugs. We will also explore how X-merge mode simulation can be used as an alternative for GLS zero-delay simulation and help in overall productivity.
|WA2.2 User Paper: Certitude for Functional Safety|
Deva Phanindra Kumar,Ranganayakulu Sri - Analog Devices Inc.
Functional Safety is becoming increasingly important in the automotive market or any other safety critical market. Better ASIL certification provides an extra edge over competition. This paper discusses simulation techniques which will help to improve functional safety and in diagnostic coverage analysis using Certitude. Certitude is not used for functional qualification purposes in these simulations but as fault injection and fault coverage tool. The proposed technique is being tested on gyroscope and accelerometer project and a case study of the same is presented in this paper.
|WA2.3 User Paper: Reconfigurable Verification Environments with Discovery VIP & Reusable Test Cases Using SystemVerilog DPI|
Yugandhar Kadiry, Naresh Duriseti - Mindspeed Technologies, Viswanath Daita - Synopsys
In this paper we will introduce a SystemVerilog-DPI based approach to create sub-system level test cases in C language. Through this we can achieve testcase re-usability at chip top level. With this approach designers can also write verification methodology independent test cases. This will immediately help in reduction of resource usage and a shorter verification cycle. We used this methodology to verify a sub-system containing Ethernet IP.
A reconfigurable verification environment is built using AMBA and Ethernet VIP for sub-system level verification. The verification environment is divided into a reconfigurable AMBA-based system and an Ethernet VIP-based system and a communication block. The paper discusses our approach, including how we could reuse the Ethernet VIP subsystem at chip top level to run the same sub system level test cases at chip top level. We will propose guidelines on how this approach can be used for projects across subsystems with different IP.
|Wednesday, June 12, 2013|
1:30 PM - 3:00 PM
|WB2: Synopsys User Session|
|WB2.1 User Paper: Handling Non-monotonic Delays in Static Timing Analysis|
Lisha Krishnan, Mohan Sultania, Debashis Sarkar - Cypress
STA methodology, being graph based, propagates the 'worst slew' at signal merging points. This means propagating the slowest transition for setup and fastest transition for hold timing based on the assumption of linear delay value dependency on input transition time.
When the linear model assumption is broken— for instance when the propagation delay decreases with increasing transition termed as non-monotonicity (as in the case of some Cypress libraries at higher transition times)—the 'worst slew' propagation results in best delays for setup and worst delays for hold. This becomes an optimistic analysis and leads to false positives in STA and silicon failure later on. Here we describe the methodology used to identify such paths and ensure correct analysis is performed
|WB2.2: TAT Improvement in Signoff Extraction using SMC Flows|
Gopinath Devarajan, Dan Prevedel - LSI
Simultaneous Multi Corner (SMC) flow enables extraction of parasitics for multiple process and temperature corners in a single run and provides significant runtime efficiency when compared to standalone extraction without sacrificing accuracy. The runtime efficiency of this flow increases with the increase in number of parasitic corners at which designs need to be signed-off. This paper quantifies the runtime benefits that can be achieved with the SMC flow and the accuracy and timing correlation results.
|WB2.3 Tutorial: Handling of Advanced Technology and Process Challenges in Parasitic Extraction using StarRC|
Advanced technologies and processes offer great benefits but also bring a lot of challenges to the parasitic extraction domain. This tutorial will cover modeling and extraction of FinFET devices, flows to handle Double Patterning and best practices for performing extraction with StarRc to optimize performance and improve productivity.
|WC2: Synopsys User Session|
|WC2.1 User Paper: Determining PLL Clock Jitter Characteristics Using XA-VCS Mixed-Signal Simulations|
Ratheesh Mekkadan - AMD
Determining clock Jitter characteristics of the PLL is important as this could cause setup and hold time violations for downstream digital logic clocked by the PLL. This could also lead to functional failures and/or performance degradation. Current methods of running transient simulations using circuit simulators for jitter characterization is extremely slow. This problem is compounded when simulations have to be run across multiple PVT Corners.
Mixed signal simulations using XA-VCS is the solution for this, especially while determining the contribution of different blocks within the PLL to clock jitter. For example, a mixed signal simulation setup of the PLL with its analog blocks (PFD+CP+LPF+VCO) in spice netlist format and digital blocks (Feedback Divider, Post Dividers, State Machines, Clock Muxes etc.) in HDL can be used to analyze the contribution of analog blocks to jitter. This paper covers mixed-signal setup, measurement techniques and performance (Cosim vs. All transistor sim) comparison.
|WC2.2 User Paper: Dynamic Electrical Rule Checking (ERC) Capability in FineSim to Avoid Hot-Spots & Achieve Low-Power Specification|
Mithun Kumar, Ashwin Nyamati - Microchip Technology India Pvt Ltd, Vivek Sharma - Synopsys
The Dynamic ERC capability or .chkdcpath feature in FineSim helps to catch dc current consumption paths. And with zgate switch enabled, the leaky path caused due to floating gates gets revealed for fixing the same. These fixes are needed to avoid hot spots or current surges in power-down mode. Without this, the issues would only be caught by testers during chip silicon testing, requiring re-spins to meet low power spec. This paper explains how FineSim’s Dynamic ERC verification methodology deployed in Microchip has helped to meet low power specification. It demonstrates the leaky paths caused due to Hi-Z Gate with real sample circuits, and also suggests possible fixes that can be implemented with ease by designers. Finally it talks about how FineSim’s performance and flexible Digital UI/cosim capabilities has helped improve the coverage by allowing both analog & digital groups to perform the Dynamic ERC checks independently, at both macro & full-chip level.
|WC2.3 User Paper: EMI & SSO simulation on board: Modelling, Analysis, And Design Solutions|
Akhilesh Mishra, Prabhat Ranjan,Yagya Dutt Mishra - STMicroelectronics
Board-level I/Os’ signal integrity and conducted EMI have become a critical concern for high-speed circuit designers, and a major cause of performance and reliability degradation of modern electronic systems. In this paper we investigate the impact of Simultaneous Switching Output (SSO) noise and propose a methodology for SSO analysis and mitigation based on IBIS 5.0 that can be seamlessly integrated into an industrial design flow. Experimental results obtained on an automotive microcontroller demonstrate the effectiveness of the proposed approach
|Wednesday, June 12, 2013|
1:45 PM - 2:30 PM
|WD2: Synopsys User & Tutorial Session|
|WD2.1 Tutorial: The Essentials for an Integrated Synplify-Vivado Design Flow Targeting Xilinx 7 Series FPGAs|
This tutorial is for FPGA designers targeting Xilinx 7 Series FPGAs (Virtex-7, Kintex-7, Artix-7 and Zynq) using Synplify synthesis and Vivado place & route. You will learn how to easily run Vivado via the Synopsys provided TCL scripting templates as well as how to drive synthesis and place and route to achieve maximum efficiency and quality of results for your 7 Series designs. Key topics that will be discussed include constraints setup, forward annotation of information to place & route, IP handling and incremental design flows. The tutorial is designed to provide practical knowledge that may be used right away on 7 Series FPGAs.
|WD2.2 User Paper: A Methodology of Automation of SoC Validation using FPGA|
Debabrata Ghosh, Felix Paul - Infineon Technologies
|Wednesday, June 12, 2013|
3:00 PM - 4:00 PM
|WA3: Synopsys User Session|
|WA3.1 User Paper: AFE Verification - A Novel approach for Mixed Signal Verification|
Neeraj Chandak, Nitin Goel, Yogesh Mittal - Freescale Semiconductors India Pvt Ltd.
As the industry is moving towards lower nodes, the integration of analog, RF and mixed signal design components in the same SoC is increasing. While the verification of the digital IPs is able to scale up viz-a-viz simulation speed and quality through constraint-driven random verification methodology, analog verification still suffers from a lack of this type of infrastructure. The conventional method for verifying the digital portion of the design (as behavioral or black box) and analog portion separately (SPICE) is not sufficient as the main verification complexity lies in checking the level of interaction between the digital and analog portions. This paper presents a novel methodology for the verification of analog and mixed-signal circuits using HVLs which improves reuse and enables automation to improve Quality Control and reduce Time to Market for SoCs.
|WA3.2 User Paper: Generic RAL Infrastructure to Address Register Verification Challenges|
Sreenivas Machavaram, Anil Kumar Sabbineni, Prashanth Srinivasa - LSI
Our approach is about a generic RAL (Register Abstraction layer) translator which is built using the powerful features of VMM for providing non-blocking access to every master. We would also mention how the Endianness switching is supported in the RAL translator so there is no need to maintain two sets of the System RDL, RALF or RAL model files for both the Endian modes. This paper also showcases how the RAL translator can be re-used at any level of verification and provides flexibility for any number/kind of interface translations. This translator has built-in support to address all the following challenges
- Multiple masters accessing same slave simultaneously using a single RAL model
- Slave has different address views for all Masters
- Sampling the register access coverage from each master using the single RAL model.
- The Endianness of the system is configurable.
|Wednesday, June 12, 2013|
3:15 PM - 5:00 PM
|WB3: Synopsys User and Tutorial Session|
|WB3.1 User Paper: The Last Microwatt - Challenges in Pre Silicon Power Estimation for Low-Power SoCs|
Accurate pre-silicon power estimation is an increasingly critical requirement in developing high-performance and ultra-low-power SoCs. Wide adoption of the UPF standard has enabled efficient design and verification of complex low power designs. However, to effectively balance the tradeoff between performance and power, it is also imperative to fine-tune CAD flows and methodologies to estimate both leakage and active power accurately up to the last microwatt. In this paper we discuss some of the key challenges that we encountered in improving the accuracy of pre-silicon power estimates, and methods we used to overcome them for low power designs. Resolution of these challenges resulted in considerable improvement in the accuracy of our Pre-Silicon power estimation.
|WB3.2 User Paper: Method for Collapsing Multiple Modes Timing Constraints |
Rajkumar Agrawal, Vivek Manikandan LSI India Research & Development Pvt Ltd
With increases in design complexity the number of STA modes has shot up. In addition, the newer process nodes have introduced a higher number of new PVT corners. These factors have contributed to an explosion in the number of scenarios for which static timing analysis (STA) needs to be performed. This has a major role in the timing signoff TAT and has resulted in a bottleneck in the design flow. One of the possible ways to handle this issue is by collapsing the number of STA modes using the approaches described in this paper. The optimal number of STA modes can be decided by user. In our implementation, we considered 3-5 as the optimal number for signoff STA modes. We also discuss the native solution for merging modes that has been made available in PrimeTime.
|WB3.3 Tutorial: Mode Merging using PrimeTime-GCA|
In designs using advanced deep submicron technology nodes, the number of multicorner-multimode analysis scenarios has increased dramatically. One approach to address these problems is to reduce the number of scenarios by manually combining SDC constraints from related input modes to generate a merged superset of constraints. However, this method is cumbersome and error-prone with the growing number of modes and can cause loss of accuracy and the generation of incorrect SDC constraints.
In this tutorial we will discuss the new feature in PrimeTime-GCA that enables automated mode merging. With this capability, you can automatically analyze and merge the input mode design constraints into a reduced set of constraints. You can then use the newly-merged design constraints to speed up timing analysis and drive ECO runs in place of the individual input mode constraints, which significantly reduces computing resource requirements with minimal impact on accuracy and runtime.
|WC3: Synopsys User and Tutorial Session|
|WC3.1 User: On Chip Adaptive Voltage Scaling to Minimize Dynamic Current Consumption|
Kumar Abhishek, Sunny Gupta, Nitin Pant, Manmohan Rana - Freescale Semiconductors
Conventionally, SoCs are timed for worst case performance. This means that critical paths are timed to operate correctly at minimum voltage and slowest devices, which can be described as the PVT (Process, Voltage, Temperature) corner. However, most of the time the chip operates in much better conditions, in terms of the three PVT parameters. Therefore, in such conditions, even the most critical paths in design will have sufficient positive slack.
We propose a solution by which we not only have enough timing slack to ensure timing is met across PVT but also reduce power consumption by making the design work at an optimal voltage by dynamically modulating the output voltage of the on-chip regulator feeding the SOG.
|WC3.2 Tutorial: Characterizing Memories and Black Boxes: Belling the Cat|
Mohamed Filzer Kummudiyil - Synopsys
Characterizing memory instances is essentially a demanding task, with its size, architecture, parasitics and features testing the limits. Characterizing complex IOs and Macros, on the other hand, poses an equal challenge with their size, complexity or black box design, operational modes, complex sensitizations and SPICE mandate requiring extreme customizations and flexibility. This tutorial talks about innovative solutions and approaches to tame thesse challenges, and churn out libraries even faster - at uncompromised accuracies.
|WD3: User and Tutorial Session|
|WD3.1 User Paper: Simplify Secure System Validation and Development: HAPS Prototyping Case Study|
Yuvaraj Ghorpade - LSI India
The hardware IP blocks which are used in secure systems have specialized data protection where the data paths are kept point to point without intermediate tap or debug points. The inherent 'INACCESSIBLE' nature of these IPs is a main challenge to build the pre-silicon validation environment. This paper is a real life case study in which the Synopsys HAPS platform was used to enable back-door entry points to simplify validation of these highly secure hardware IPs or systems.
|WD3.2 User Paper: Challenges in Mapping Multi-core A15 ARM Processor on FPGA|
Doug Hogberg, Badri Seshadri - NVIDIA
Feature-rich multimedia devices in mobile application processors require complex SoC designs to meet market demands for high performance and energy consumption. Consequently, the demands by the high-end applications are mostly met by multi-processor SoC architectures. These feature-rich mobile ASIC designs and a short time-to-market schedule pose big challenges for FPGA partitioning/routing/bring-up on these designs. In this presentation we`ll cover how we overcame the design complexity of mapping the CORTEX-A15 multicore processor on an FPGA system with a mix of VIRTEX5/VIRTEX6 FPGAs used as a prime vehicle for early software development. The paper focuses on design partitioning across multiple FPGAs, proper synthesis constraints, and handling routing issues leading to runtime reduction of netlist generation for initial design bring up and debugging design issues on the FPGA. The presentation will also cover the aspects of handling cross talk and issues around Virtex6 and Virtex5 inter-usage.
|WD3.3 Tutorial: My BFF FPGA-based Prototyping Solution: Better, Faster and Flexible |
With growing design size and complexity and a need for high performance, deciding which FPGA-based prototyping solution to choose is critical in the product development process. Do you build a custom board OR decide to try to eliminate development risk by adopting a commercial system? In this tutorial Synopsys experts in FPGA-based prototyping showcase the next generation HAPS-70 system and the key automation features that make commercial prototyping solutions attractive.
In this tutorial, you will learn:
- How the enhanced HAPS Trak 3 I/O connector technology with HSTDM delivers up to 3x performance improvement in data throughput over traditional pin multiplexing
- How to accelerate multi-FPGA partitioning by up to 10x as compared to manual methods
- How the modular system architecture of the HAPS-70 systems scales from 12-144 million ASIC gates to accommodate a range of design sizes, from individual IP blocks and processor sub-systems to complete SoCs
|Wednesday, June 12, 2013|
6:00 PM - 8:00 PM
|PrimeTime Special Interest Group (SIG) Dinner|
Synopsys hosts worldwide annual events for the PrimeTime Special Interest Group, providing an opportunity for PrimeTime users and design engineers to stay connected with the latest developments in the field of Static Timing Analysis (STA). We are pleased to host this PrimeTime SIG event at India SNUG 2013. This time the event will feature a technology panel of timing leaders from various fields. Panelists will share their vision and experience on advanced ECO methodologies that accelerates design closure on the most advanced technology nodes. There will be a Question and Answer session at the end of the presentations for direct panelist-audience interaction. This event is open to Synopsys PrimeTime users and engineering managers.
|Thursday, June 13, 2013|
9:00 AM - 10:15 AM
|The Role of Intelligent Silicon in Addressing Data Deluge Gap|
Raman Santhanakrishnan - LSI India R&D Pvt Ltd
We live in a data-centric era, a world where numerous and simultaneous mega trends like social platforms, smart clients, mobile broadband internet, video and the cloud are resulting in exponential growth in the creation, storage and sharing of data. As machines begin to talk to machines, this trend is accelerating even further. The resultant "data deluge" gap created by this trend can only be successfully addressed by "Intelligent Silicon". Silicon that has been a key catalyst for innovation, the foundation for cloud infrastructure (includes client devices, mobile network and the datacenter) enabling breakthrough processing speeds, dramatically reduced power and size, tremendous cost savings, efficient data transfer and storage. What does "Intelligent Silicon" mean? What are the major requirements on such silicon and how are those met? As the relentless pressure on cloud infrastructure continues, how do we design and deploy intelligent silicon that addresses these future needs? What kind of design methodologies, IP and technology requirements are unfolding in front of us to meet them?
In this presentation, Santhanakrishnan Raman talks about these important drivers and describe how we are positioned to deliver the intelligent silicon that the data-centric era deserves.
|Thursday, June 13, 2013|
10:30 AM - 12:30 PM
|TA1: Synopsys User and Tutorial Sessions|
|TA1.1 Tutorial: Design with FinFET & Double-Patterning, a Brief History of the Future|
While planar transistors have worked well from 100 microns down to 20 nanometers, revolutionary, non-planar transistors such as FinFET offer superior attributes and demonstrate much better results in terms of performance, static and dynamic power at 14 nanometers and beyond. However, although FinFET is considered as the most promising device for emerging technology nodes, it introduces new design complexity for IP development, electrical simulation, RC extraction, and physical verification. Even interconnect is undertaking a revolutionary evolution: the last pitch manufacturable using immersion lithography with single exposure is 80 nanometers; starting at 20 nanometers, double-patterning is required as we wait for EUV availability, and might be replaced by triple- and even multi-patterning at 14 nanometers and beyond; like FinFET, double-patterning introduces new design complexity for IP development, and physical implementation and verification. Please, join this session to hear what EDA is doing to hide unnecessary details, whilst enabling designers to get the most out of these emerging technology nodes.
|TA1.2 User Paper: Physical Design Challenges of a High-performance FPGA in 22nm Process Technology |
Aravind Karanth, Veena Radhakrishnan, Madhusudan Rajagopal, Namit Varma - Achronix Semiconductor Corporation
This paper describes the physical implementation and verification challenges of a 432mm2, 6 billion transistors, high-performance FPGA chip, designed in 22nm 3-D tri-gate process technology. With a large central macro surrounded by multiple high-speed interface blocks with highly skewed aspect ratios and a channel dominated fullchip, the implementation challenges were many. The fullchip, as well as the blocks, had multiple synchronous clocks leading to very tight clock balancing requirements and semi-custom CTS implementations. High block-level port counts led to innovative routing solutions at fullchip. Blocks with huge feed-through data & clock busses, with perpetually changing IO timing requirements, were a major challenge for timing closure. The paper also goes into details of the fullchip physical integration & physical verification challenges faced, given the large die size and 22nm tri-gate transistor technology.
|TA1.3 User Paper: Floorplanning is an ART and with DFA You are an Artist!!|
Hardeep Singh , Veena Venugopalan , Sarvesh Verma - LSI India Research and Development Pvt. Ltd.
Design complexities have unearthed a detrimental dependency of quality-of-results on the design’s initial Floorplan. With the classification gap among designers as RTL and physical designers, the latter generally do not have visibility into the design’s high-level Data Flow model, which has a potential impact on floorplan. Therefore, physical designers can squander precious time and resources to bridge this gap and understand how to arrive at an optimal floorplan, eventually impacting their efficiency and design cycle time. Synopsys bridges this Data Flow model awareness gap , with its Data Flow Analysis (DFA) technology, which equips and empowers physical designers with data flow knowledge through a set of analysis and exploration tools for tasks like macro placement, macro interactivity with logic and IO resulting in quicker and optimal floorplans. This paper highlights the 3X design cycle time gain and improved QoR, using DFA technology on our Macro & Memory intensive designs over conventional methods.
|TB1: Synopsys Tutorial Sessions|
|TB1.1 Tutorial: Addressing Low Power Verification Challenges with VCS |
Nowadays power consumption is a main concern which is influencing each and every aspect of the design flow. Advent of Low Power requirement adds multi fold complexity to already complex verification problem. Design community is using IEEE 1801 standard (UPF) for capturing the power intent of the design which is used across all the phases of design development. Low Power RTL dynamic simulation plays a key role in validating the power intent and design together. This tutorial provides insight into range of commonly used low power techniques, UPF way of capturing the intent and simulating the power intent with RTL. It will also provide insight into the available debug infrastructure with MVSIM-NLP simulator.
|TB1.2 Tutorial: Transaction Level Verification with Zebu Server |
In this tutorial you will learn what transaction-level verification means in general and specifically how it applies to the ZeBu-Server emulation platform. Transactors offer a unique combination of performance, accessibility, flexibility and scalability, while providing a realistic system-level test environment for the DUT. The tutorial will describe the inner workings of a transactor with emphasis on the advantages and tradeoffs compared to alternative approaches. Step-by-step instructions for creating a transactor will be provided, including an introduction to a high-level SystemVerilog behavioral language/compiler, called ZEMI3, conceived for automating the generation of a transactor.
|TC1: Synopsys User and Tutorial Sessions|
|TC1.1 Tutorial: Low Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs|
For many mobile devices, low power video processing is critical to product success. To enable a great experience with long battery life, designers are offloading demanding video processing tasks from the CPU and mapping them to embedded GPUs that work in parallel. But how many GPUs are needed? Which mapping is best? This tutorial features Synopsys Platform Architect to explore HW-SW partitioning and mapping of a real-time video encoding algorithm for optimal system performance and power.
|TC1.2 User: Integration of Synopsys DesignWare DDR Controller & DDR3/2 PHY IP in 28nm|
Girish Karanam, Ashish Veeramaneni - Open-Silicon
This tutorial presents an overview of the steps and challenges involved in integrating the Synopsys DW DDRx Memory Controller(uMCTL) and DDR3/2 PHY in 28nm. It presents an overview of how different pieces of IP- both Hard & Soft – were configured and taken through different phases to integrate them into the SOC. This tutorial will also talk about the key items required to be checked for optimal DDR IO Padring implementation during the Back-End implementation of the PHY in the top level design.
|TD1: Synopsys User and Tutorial Sessions|
|TD1.1 User Paper: Dynamic Power Optimization Techniques for Highly Switching Design In Physical Implementation|
Devendra Deshpande, Shaibal Kavdia, Mayank Mittal - LSI India Pvt Ltd
All current design flows focus on timing-driven implementation, which invariably leads to an increase in dynamic power dissipated by the chip. This can lead to an increase in system costs and other complexities and hence, needs to be taken care off during the implementation process. This paper describes various factors and the techniques that can be integrated into a physical implementation flow to reduce dynamic power. Using these techniques, 16% power reduction was achieved for a 140M design in 28nm.
|TD1.2 User Paper: Efficient Methodology for Leakage Optimization with Synopsys Tools |
Jürgen Karmann, Ravikumar Rajendraprasad - Infineon Technologies India PVT Ltd.
Leakage power is a significant contributor to total power, which grows exponentially at high temperatures. A very effective measure to reduce leakage is to swap high performance cells with low leakage cells, wherever timing closure allows. A new functionality in PrimeTime-ECO allows swapping cells on sign-off timing. The assessment of the different solutions showed that the amount of leakage power saved can be significantly improved by a proper methodology with reduced number of iterations. This new functionality of PrimeTime-ECO will be presented along with design implementation flow methodology which shows an improved leakage optimization as well as better tool runtime.
|TD1.3 User Paper: Handling Nested Power Domains in Complex SoC|
Shashank Bhonge, Vaishali Huilgol, Vinod Kumar Reddy - Xilinx
This paper describes the challenges faced and resolutions proposed during RTL2GDSII implementation of a high-performance hierarchical complex SoC design with nested power domains. To optimize power at all levels, different power strategies were employed such as multi voltage domains, shutdown, always on domains. It highlights the approaches followed in handling hierarchical UPF for a MIM (Multiple instantiated Module) design and insertion of power cells along the flow with the nested ILM structure. Challenges with handling power switch network along with the design requirements are discussed at length in this paper.
|TD1.4 Tutorial: Unlocking the Low Power Potential of your Chip – An Advanced Flow Methodology using UPF2.0|
As designs transition across technology nodes, reducing the power consumed by the chip requires designers to employ various Low Power techniques throughout the design cycle. This coupled with the current design sizes and complexities, forces designers to use Hierarchical Implementation approaches, which poses a harsh challenge when it comes to managing the number of UPF versions used. In this tutorial, we bring to you the flexibility and advantages of using UPF2.0 constructs and their application in Hierarchical flows, both Top Down as well as Bottom Up. We also exhibit some key considerations that designers should employ while designing or choosing their Low Power Libraries and present some new tool features and tips that will help simplify your overall Implementation and Verification methodologies.
|Thursday, June 13, 2013|
1:30 PM - 3:00 PM
|TA2: Synopsys User Session|
|TA2.1 User Paper: Optimization Techniques for Designing a Channel Dominated High Activity Multimillion 500+Sq mm Chip|
Anurag Mishra - LSI R&D (India) Pvt. Ltd. Vineet Kumar Kothari - Synopsys
With innumerable applications becoming viable through chip design, we’re seeing an inception of complex and efficient designs on board. For such uniquely challenging designs conventional techniques alone may not offer optimal results. This necessitates innovative solutions to meet design closure criteria with minimum TAT.
The design under discussion measures around 500 sqmm, has 120M+ gates with upf and 55 partitions with intricate intercommunication between them. Result: A channel dominated floorplan with multiple nets of varying length traversing through the channel. This in turn, contributed to significant increase in chip power. Also, higher signal interconnects demand larger DECAP area to meet IVD requirement. Hence, the design needed out-of-the-box optimization techniques to deliver better QoR and run-time, while simultaneously meeting other specifications. In this paper, we will discuss the challenges posed by the designs of such size and complexity and elaborate on pioneering optimization techniques to address such challenges
|TA2.2 User Paper: In-Design 20nm Physical Verification Closure Within ICC Using ICV|
Siddika Gundlur, Hemasundar Pethakamsetty - AMD India Pvt Ltd.
As technology scales down to 20nm , the number of complex DRC including the emergence of DPT rule checks to achieve acceptable manufacturability are increasing, leading to an increasing number of violations after routing phase. Fixing post-route violations manually is time consuming thus affecting the tape-out schedules. In-design physical verification of IC Validator brings the power of full signoff physical verification constraints into the design phase without imposing time-consuming stream-in and stream-out process. Using in-design PV, DRC and manufacturing issues are caught much earlier in the design cycle, eliminating late-stage surprises close to tape-out. IC-Validator’s pattern-matching technology eliminates the need for convoluted rules and, with almost zero runtime penalty per pattern, it significantly speeds up the time to achieve manufacturing compliance. This paper presents how In-Design physical-verification and fixing with in ICC-ICV interface at 20nm, helped to reduce TAT between Physical-Implementation and Signoff Physical-Verification phases thus reducing tape-out schedule.
|TA2.3 User Paper: Multi-Pronged Approach to Address Nanometer Physical Verification Challenges |
Complexity in nanometer-processes requires radical improvements over the way physical-verification was handled earlier. Physical-verification tools need a different approach to handle increased complexity in DRC, LVS and reliability checks. Physical-verification approaches that were successful earlier are no longer scalable by merely increasing compute infrastructure.
Topics covered include:
- New features that were brought into layout-verification to handle complex nanometer rules
- High-level language features to achieve higher programmability including API, remote and user-defined functions.
- LVS ease of use with multiple connect sections, user interface for device extraction, improvements in dimensional, ERC checks
- Runtime and improvements in debug assistance in DRC and LVS run environment.
The paper also discusses the mysql error database and features in detail to support better debug. Overall, this paper covers different aspects incorporated into advanced physical-verification tool to overcome sign-off problems caused due to process, design complexity in sub-micron design nodes.
|TB2: Synopsys Tutorial Session|
|TB2.1 Tutorial: Advanced Verification Debug Productivity with Verdi3 and Siloti |
In this tutorial, you'll learn how to maximize your productivity by using Verdi's Transaction Based Debugging technology to correlate and visualize the software "events" with the corresponding hardware "transactions" and browse, trace, and debug transactions. You’ll learn how the tool's vertical correlation allows you to take the debug to the signal level waveform while retaining all of the necessary debugging details.
This tutorial also provides insight into debug solutions that adequately address efficient debugging of the range of low-power techniques - from simple power-gating to retention technique to low power sequences in dynamic simulations. It also discusses how low power coverage and its visualization can help determine the completeness of the verification effort. Siloti records the essential signal data needed from logic simulation to achieve full visibility into the functional behavior. This minimizes simulation overhead and can then be used with Verdi system for more efficient debug and analysis
|TC2: Synopsys User Session|
|TC2.1 Tutorial: Designing IP for FinFET Technology: The Opportunities and Challenges|
Although planar CMOS technology continues to scale to 20-nanometer (nm) and beyond, FinFET technology offers superior attributes and demonstrates better results in the areas of performance, leakage and dynamic power, intra-die variability and retention voltage. Although FinFETs are emerging as the device technology of choice at these advanced nodes, they introduce new design challenges for IP development, which require knowledge of and experience in designing with FinFETs to ensure design success. Join this session to understand the benefits and challenges of transitioning from planar to FinFET technologies and how IP plays a significant role in this transition.
|TC2.2 User Paper: Synopsys Virtual Prototypes for Pre-Silicon Software Development - Texas Instrument’s Latest Experience|
Vishal Goel , Asiful Mondal - Texas Instruments, Mojin Kottarathil - Synopsys
The significance of Virtual Prototyping in SoC development is well appreciated but it is the life cycle of a complex Virtual Prototype that constitutes the content of this paper. This paper describes TI's recent development of virtual prototypes for two key SoCs of great complexity using Synopsys’ virtual prototyping tools. Challenges faced included re-use of models across tools, TI specific debugger integration and interoperability with third-party debuggers such as Lauterbach’s TRACE32.The paper also puts some emphasis on a need for further standardization in the SystemC community.
This paper will describe how Synopsys tools are helping to minimize the complexities of Virtual Prototypes creation, where IP models from several third-parties are involved. It also mentions how various features of these tools are helping to accelerate pre-silicon software development. Technologies like hybrid prototyping and some unification of tools towards the Eclipse framework are also discussed in this paper.
|TD2: Synopsys User & Tutorial Session|
|TD2.1 User Paper: Novel Low Power Static Checking Methodology now Integrated in MVRC|
Neha Agarwal, Nitin Kaushik - STMicroelectronics Pvt Ltd, Patrick Blestel, Stephanie Varela - Synopsys
Power management has become a critical factor especially in design of wireless and handheld devices where various advanced techniques of low power reduction are employed. Implementation tools are able to keep pace with this increasing complexities but do have certain pitfalls which need to be identified and corrected using appropriate verification methodologies. In our design, we used the Synopsys solution MVRC (Multi Voltage Rule Checker) right from RTL up to the signoff stage. In close collaboration with Synopsys, we were able to integrate checks for Bias Rail order which is critical to identify the correct usage of Always ON cells in the design and also some Leakage checks which ensured the correct usage of LS/ISO cells. Apart from this, we also provide some useful recommendation and enhancements that can be incorporated in the flow to ensure smooth implementation of any Low Power design.
|TD2.2 Tutorial: Next Generation Static Verification Platform (Verdi Signoff) - Low Power|
As design sizes and complexity grow tremendously over the years, engineers are always hard pressed with time-to-market concerns. The current static verification tools are running out of steam as convergence is driving the growth in SoC complexity and point tools are not able to scale up. Verdi Signoff is the next generation platform architected to meet the growing static verification challenges of customers. In this tutorial, we will introduce users to the benefits of platform centric static verification and focus mainly of Verdi Signoff-LP (VS-LP), the low power application of the Verdi Signoff platform. This tutorial provides insights into VS-LP’s advantages, integration into design flows, the suite of low power checks, the debug infrastructure before detailing the differentiating features of VS-LP
|Thursday, June 13, 2013|
3:15 PM - 5:00 PM
|TA3: High-Performance Cores|
|TA3.1 User Paper: Synthesis Techniques for Faster Design Closure of High Performance Quad Core Processor|
Neha Agarwal , Kuldeep Chahal, Sagar Malhotra - STMicroelectronics Pvt Ltd.
Quad core ARM subsystem is a very complex IP from a design closure perspective. High-performance target along with tight area and power requirements are typical. In our case, the complexity was compounded by the special logic addition requirements at L2 cache.
To overcome these challenges and for faster design closure, we needed to take concrete steps starting from the synthesis stage itself. The DC-SPG synthesis flow by Synopsys came to our aid by way of superior placement aware synthesis. However, on complex designs such as the one in question, some further tweaking is required in the flow, the techniques/strategies to achieve this will be discussed.
|TA3.2 User: GHz ++ : A Step by Step Tutorial on Recovering That Extra Picosecond|
Krishna Kant Verma - Qualcomm, Deepti Pookat - Synopsys
Here we will discuss the best practices discovered during the implementation of multi-core high performance cores using IC Compiler. This presentation outlines some novel approaches that were deployed at different stages of the physical design flow for much faster timing convergence, beating the tightest tape out schedules. The approaches included items in the data preparation, synthesis, DC to ICC correlation, floorplanning, data flow analysis, clock enable fixing, CTS, routing and last mile timing closure based on signoff analysis.
|TA3.3 Tutorial: Engineering Trade-Offs in the Implementation of a High-Performance Dual Core ARM® Cortex™-A15 Processor|
ARM and Synopsys
Learn about the engineering trade-offs and flow development process to balance gigahertz+ performance and low power on a dual-core Cortex-A15 MPCore™ processor implementation. This tutorial will highlight best practices and technologies from the Galaxy Implementation Platform to meet challenging performance targets, while minimizing leakage power. Synopsys' high-performance core (HPC) methodology will be demonstrated through a reference implementation of a dual-core ARM Cortex-A15 processor with ARM POP™ technology for core-hardening acceleration on TSMC 28HPM process. Technologies featured include physical guidance for a predictable implementation flow, transparent interface optimization for faster top-level closure, and final-stage leakage recovery for reduced leakage power. The final product is a strong starting point for designing the 'big' core in a big.LITTLE™ technology-based SoC, or as a stand-alone application processor for high-end mobile markets.
|TB3: Synopsys Tutorial Session|
|TB3.1 Tutorial: Certitude for Functional Qualification|
Verification engineers continually struggle with questions related to verification effectiveness. Do my test scenarios exercise the functionality sufficiently? Is my checker and assertion infrastructure complete? Traditional coverage techniques only determine if you’ve executed all lines of code or whether you’ve exercised all important functionality that you have defined. This analysis may not be sufficient, and there is no objective measure of "completeness". This session will explain how Certitude Functional Qualification augments traditional coverage to provide unique insight into the quality of simulation and formal verification environments. Certitude's proprietary mutation-based process inserts "artificial bugs" or faults into the design and measures the ability of the verification environment to detect these faults. The results of this process provide an objective measure of overall verification quality and identify specific holes and weaknesses that can allow RTL bugs to slip through the process.
|TB3.2 Tutorial: VCS Technologies for Improved Performance and Productive Analysis|
This tutorial will focus on several technologies recently added to VCS that dramatically improve simulation, debug and analysis productivity. Checkpoint and interactive rewind, , Partition Compile and PreCompiled IP for improved Turn Around Time for iterative analysis and recompilation would enable increased producytivity. Dumping and browsing of dynamic/testbench objects , analyzing complex object relationships, UVM, VMM, OVM components are now easily enabled. Recent improvements to the DVE Constraint GUI allow graphical constraint debug, what-if analysis and distribution-debug to be performed.
|TC3: Synopsys User and Tutorial Session|
|TC3.1 Tutorial: Ease Debug and Control of Network Software using Virtual Prototypes to do Full System Simulation|
The software communication overhead in networking applications continues to grow. This makes it imperative to bring up the software as early as possible in the context of a full system to both reduce the overall development and debug cycle and to make sure that the setup can be tested in a realistic setting. In this tutorial we will show how you can use a virtual prototype with a DesignWare Gigabit Ethernet model and ARM processor models to simulate a network application like a server farm. We will show how the virtual prototyping methodology not only enables software development before hardware availability, but also helps reduce the actual development and debug cycle. We will go on to show how virtual prototypes allow software developers to keep an overview of what software tasks are going on at any given time and create predictable test suites for this type of complex design.
|TC3.2 User Paper: Virtual Prototype for Infineon MCU Using Synopsys Virtualizer|
Prasanna Venkatesan Kesavan, Simranjit Singh - Infineon Technologies India Pvt Ltd., Indraneel Mondal, Prakash Sahay - Synopsys
Virtual Prototyping provides an answer to the complex verification problem by enabling early software development and early HW/SW verification. The Virtual Prototyping solution allows scalable fault injection and error condition testing and provides fast simulation speeds along-with high timing accuracy enabling flexible and efficient software verification and performance analysis. Infineon has a multi-core based high-performance MCU intended for Automotive Powertrain applications. A Synopsys Virtualizer based virtual prototype for the Infineon MCU allows full system simulation in closed loop with built-in interfaces to Vector CANoe, Matlab Simulink and Synopsys Saber tools.
This paper presents the Synopsys Virtualizer based Infineon AURIX platform, the concept of Virtual Hardware In the Loop and how to perform hardware and software analysis using the Virtualizer platform. This paper highlights the advantages of AURIX Virtual platform and the configuration procedures.
|Co-Simulation - An effective technique to optimise Simulation Speed|
Jayashri Abm, Shishira M Pareppady, Ray Schuppe, Priya Ananthakrishnan, Vijay Bagalad - IBM
|Timing Report Pyramid – Something for Everyone|
Tripurasundari Sundaresh, Lisha Krishnan, Shankar N. Pushpendra Yadav - Cypress Semiconductor
|Scalable, Configurable, Reusable (SCORE) Test Bench Using UVM & Advance Debugging Techniques Using DVE|
Peer Mohammed, Naveen Yanamadala, Vinay Kumar Vedula - Mindspeed, Parag Goel - Synopsys
|Embedded Memories and Readiness of ESP-CV for 20nm and Beyond|
Prakhar Raj Gupta, Rashna Seli -ST Microelectronics, Rakesh Shenoy - Synopsys
|Dynamic Template C eation Using ICV for Physical Design Methodology Checking|
Anand Kumaraswamy, Pardeep Saini, Harshit Agnihotri - IBM
|Dynamic Power Reeduction Using XOR Self-clock Gating Methodology|
|SystemC / TLM model of Audio Codec|
Parvinder Pal Singh, Shabarish Sundar, Archna Verma, Umesh Sisodia - CircuitSutra Technologies
|Methodology for signoff convergence and smooth SoC integration of high performance partition|
Anuj Soni, Kumud Kakati. Prashant Sharma. Shrinivas Sureban - LSI Technologies