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| AMS |
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SPICE Level Verification of Full Chips When Digital Verification is Just Not Enough!
Sandip Atal, Fabio Carlucci, Ashish Kumar Gupta, Rohitaswa Bhattacharya, Luca Buratti [ST Microelectronics], Rakesh Shenoy [Synopsys] |
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Performance Evaluation of Statistical Eye Simulation (StatEye) in HSPICE for Backplane Systems
Sivagurunathan, Sam David, Pramitha [Wipro Technologies] |
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SRAM Compilers Timing Analysis Using Active-Net Based HSIM-Star-RCXT Flow
Gaurav Varshney, Dharin Shah, Parvinder Rana, Sateesh Chandramohan [Texas Instruments India Pvt Ltd] |
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Synopsys HSPICE Based Automatic Standard Cell Circuit Generation
Lakshmi Jain, Niharika Kishore, Nimmida Abdulsalam, Sunitha S [Wipro Technologies] |
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XA: A Case Study of PLL and ADC Verification
Premraj Rajasekharan Nair, Lakshmi Govindankutty [Wipro Technologies] |
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Using "Divide and Conquer" to Address Tight Deadlines of Electromigration Flow
Atul Bhargava, Bharat Bhushan, Neeraj kapoor, Tushar Sharma [ST Microelectonics] |
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Power Management & Behavioral Model Checks in Co-simulations Using VCSMX-NANOSIM Tool
Ashwin Nyamati, Rajeev Suvarna, Ravi Kumar Reddy [Wipro Technologies] |
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Custom Macro Characterization and STA Using Nanotime
Basudeva Dash, Amit Didwania, Vineet Puri [Infineon Technologies] |
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Synopsys' Custom Design Solution
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Utilizing & Understanding HSIM for Performance & Accuracy Tuning
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| FPGA/IP |
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Efficient Emulation Methodology of Multi-Million Gate SoCs Using Synopsys FPGA Tools
Sabyasachi Dey, Praveen Goyal, Ankit Srivastava [Qualcomm India Pvt. Ltd.] |
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Verifying Complex SoCs Using FPGA Based Prototypes
Vijay Chachra [LSI India Pvt Ltd] |
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Prototyping of SoC Design for Wireless USB applications on HAPS-54 Platform
Subramanian Parameswaran, Manish Kumar Saxena, Jagonda Balgonda Patil [Samsung India Software Operations] |
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Hardware Assisted Verification Techniques
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| Physical Design |
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A Pseudo-Hierarchical Place and Route Flow Approach to Handle Design Disparities
Raashid Shaikh, Santhosh T, Arathy M [Texas Instruments India Pvt Ltd], Anshuman Anand [Synopsys, Inc.] |
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Cost Efficient Implementation of High Performance, Low Power Designs
Ravishankar B, Vithal Ambi, Ravneet Singh [LSI India Pvt Ltd], Subrata Kumar Sen [Synopsys, Inc.] |
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Best-in-class Clock Tree Power on a 45nm High Density TI IP
Hari Krishnamoorthy [Texas Instruments India Pvt Ltd], Harissh Swaminathan [Synopsys, Inc.] |
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Routing at Advance Process Nodes to Improve DFM/Yield, QoR, Power, Runtime Using ICC Zroute
Pradeep Kothari, Praful Gaikwad [AMD India Pvt Ltd], Kodur Narsimha Reddy [Synopsys, Inc.] |
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Implementation of ARM® Mali™- 400 MP Graphics Processor Using MIM and ILM of Synopsys Galaxy Platform
Vikram Kuralla [ARM Embedded Technologies Pvt. Ltd.] |
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A Comprehensive Flow for the Implementation of Large and Complex Multimedia Designs in 45nm and Beyond
Sreeram Chandrasekar, Aishwarya Singh, Gowrysankar Shanmugam, Anup Rajput, Amitesh Khongal [Texas Instruments India] |
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Advanced Implementation techniques for closing timing critical processor using ICC
Deepti Miyan, Ashish Khurana [ST Microelectronics] |
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Evaluating ICC-DP as a FloorPlanning for a Complex Hierarchical Design
Maria Martin, Srinivas P, Sridevi Warrier [Analog Devices India Pvt. Ltd.] |
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Clock Mesh in IC-Compiler
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IC Compiler Design Planning Highlights
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Hierarchical Flow/Clock Tree Mesh Updates
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| Signoff |
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Methodology to Verify and Debug the Quality and Completeness of Constraints
Sujit Jadhav [LSI India Pvt Ltd], Vikas Choudhary [Synopsys, Inc.] |
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Challenges and Solutions Towards 40nm Timing and Reliability Signoff
Rajagopal KA, Vidit Babbar, Ashwini Gopinath, Palkesh Jain, Ajoy Mandal, Prateek Thakyal, Prashant Soraiyur [Texas Instruments India Pvt Ltd] |
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CCS Flow for Accurate Timing/Noise Closure for 65nm and Below
Raghavendra.V [Open-Silicon] |
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Signoff Crosstalk Noise Analysis Using PTSI - A Methodology Perspective
Gopinath Venkatesh, Prashant Soraiyur, Rajagopal K.A, Vidit Babbar [Texas Instruments India Pvt Ltd] |
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Methodology to Deal With UITE-461 for Clock Dividers
Azad Singh [ST Microelectronics] |
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Comprehensive and Accurate Capacitance Extraction Solution Using Star-RCXT/Raphael-NXT
Nischal S, Ashwini Gopinath, Shailendra Dhuri, Pankaj Goinka, Arvind NV [Texas Instruments India Pvt Ltd] |
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An Approach to Hierarchical Multi-Voltage Noise Analysis Using PT-SI with Minimal Runtime-Accuracy Tradeoff
Chakradhar Tallury, Vijay Kumar Budumuru, Vijaykishan Narayanan [AMD India Pvt Ltd] |
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Lynx - Improving RTL to Design Efficiency
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Advanced On-Chip Variation
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| Synthesis |
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Synthesis Techniques for Formal Equivalence Closure in Timing Critical Designs
Ashish Mishra [Qualcomm], Anantha Bhat [Synopsys, Inc.] |
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Synthesis Of Ultra High Performance Designs
Budumuru Vijay Kumar, Chakradhar Tallury, Shyam Jagini, Arun Iyer [AMD India Pvt Ltd] |
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Accelerating Design Closure using DC-Graphical and ICC
Suresh Raman, Srivatsa Srinath [Intel Technologies India Pvt] |
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Fanout and Statistical Power Estimation based Minimal Scan Cell Gating for Low Test Power Consumption
Vishwanath.S, Mohammed Ashfaq Shukoor, Srinivas Kumar Vooka, Srivaths Ravi [Texas Instruments India Pvt Ltd] |
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Congestion Prediction and Optimization Using Design Compiler Graphical
Jayesh K Vijayan, Rajani D, Praveen Kothanath [Wipro Technologies] |
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Synthesis Strategy Trend of Current SoCs: Practices and Challenges
Mayank Jindal, Deepak Saraff, Sarveswara Tammali, Manasi Gokhale [Texas Instruments India Pvt Ltd] |
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Techniques for Achieving Higher Completion and Verifying Low Power Designs in Formality
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Accelerating Design Closure
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| Verification |
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Gate Level Verification of Multi-Voltage Design
Ravi Kanth Aluru, Sambhav Jain, Ashis dash [Nvidia Graphics Pvt. Ltd.], Vishwanath Sundararaman [Synopsys] |
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Verifying Complex Low Power Integrated Graphics Chip: A Methodology Using MVSIM and MVRC
Girish Kumar S, Alok Jain [Nvidia Graphics Pvt. Ltd], Sesha Sai Kumar C V, A. Krishna Theja [Synopsys, Inc.] |
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RTL and Verification Challenges and Changes for Low Power Design Verification Using MVSIM
Narasimha Karunakar, Harpreet Arora [AMD India Pvt Ltd], Vikram Malik [Synopsys, Inc.] |
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Guided Convergence Towards Verification Closure Using VMM Planner
Pritpal Singh Hira, Amarjeet [Freescale Semiconductors], Mayank Digvijay [Synopsys, Inc.] |
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Methodologies for Complex SOC Verification
Pradeep Babu, Rahul Maitra [Texas Instruments India Pvt Ltd], Prathamesh Joshi [Synopsys, Inc.] |
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Designing Low Power WLAN Chips - The UPF Way
Venkateshwarlu V [Redpine Signals, Inc] |
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Autogeneration of Config Generator, Transactor, SV Assertions and Coverage From Register Specification
Ravitej Sriram, Ashish S Hegde [Nvidia Graphics Pvt. Ltd.] |
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Improving Verification Quality & Confidence of a Bridge Design Using Assertion IP's and Hybrid Formal tool Magellan
Aneet Agarwal, Divya Dhiran [Texas Instruments India Pvt Ltd] |
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Hierarchical System Level Test Bench Development Using VMM - SV
Shankar. S, Syed Sheeraj. G, Venkata Suresh, Babu. M, Murali Krishna. A [Cypress Semiconductor Ind Pvt Ltd] |
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HW-FW co-simulation using SystemVerilog TestBench
Vikram Bichal, Srinivas Reddy B, Sridhar Kotha [Brocade Communications] |
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Faster Verification Closure Using VMM and DesignWare VIP's
Anup Aprem, Sajeev Thomas [Analog Devices Pvt. Ltd.] |
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Multi Voltage CPU Design Verification - Power Intent Extraction Flow
Balakrishna Mohan Kanukollu, Veera Pradeep Pasupuleti [AMD India R&D Centre Private Limited] |
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Approach to Verifying a Design for Robustness to Errors in a Constrained Random SV/VMM Environment
Kauser Rabbani, Manikandan Chandrasekaran, Atul Kalambur [Nvidia Graphics Pvt. Ltd.] |
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Assertion-Based Verification of Mixed-Signal Behaviors with Sampling Clock
Subhankar Mukherjee, Subrat Panda. Pallab Dasgupta [IIT Kharagpur] |
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Multi Voltage Verification for High End Mobile Processor Design
Jianfeng Liu [Samsung Electronics] |
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DFT Verification Flow Improvements - Needs and Results
Prasanth V, Rajesh Kedia, Milan Shetty, Srihari Mallavarappu [Texas Instruments India Pvt Ltd] |
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Coverage Driven Verification Environment For WLAN MAC System: A VMM Based Approach
Joice George, Praveen S R, Shilpa Prakash, Vasudev Srinivasan [Wipro Technologies] |
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VMM - Low Power
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