SNUG Germany 2014 Abstracts  

Tuesday, May 14, 2013
10:15 AM - 11:45 AM
A1 - Front-End Implementation - Advanced Synthesis
Applying Synopsys Physical Guidance (SPG) Methodology to Address Complex 28nm Design Challenges
Jürgen Dirks - LSI
With ever shrinking geometries in latest technology nodes the cell placement is a critical factor that affects routing, thus a non-optimal placement and routing negatively impacts timing closure and power consumption. A methodology to overcome these issues is the Synopsys Physical Guidance (SPG) flow, which was added to the physical design tool suite to get close correlation between floor plan aware synthesis in Design Compiler and layout in IC Compiler.

After a brief introduction to the Synopsys Physical Guidance technology the present paper outlines the usage within flows applied to real-life designs. An SPG design flow is presented which covers the use of different tools for synthesis, test insertion and layout, showing the flexibility allowing to incorporate other 3rd party tools. Already within the synthesis environment aspects like general routability improvements are highlighted. Solutions to specific congestion issues as well as power consumption reduction are shown and results compared to non-SPG synthesis and layout flows.

Formality 2013.03 Update and Hierarchical UPF Flow
David Low - Synopsys
This tutorial presents the latest advancements of Formality to help you achieve best-in-class equivalence checking while allowing the highest quality of results from Design Complier . The discussion will cover highlights of the 2013.03 release including improved completion for challenging designs, new hierarchical verification capabilities, faster RTL to gate performance, and other enhancements. The session will also discuss the latest enhancements and recommendations for deploying a hierarchical UPF flow.

Target Audience:
This is an informative session that will be applicable to all Design Compiler and Formality customers

A2 - Backend Implementation - Advanced Applications
Achieving Timing Convergence by Resolving Congestion and Improving Clock Skew
In this paper we take a look at one of the blocks from our next-generation chipset. This block is an 800k instance design with many macro cells, tight timing constraints of nearly 1 GHz clock and difficult die size requirements. In order to meet these constraints, we had several challenges on the design and had to work though several iterations of the floorplan and CTS (Clock Tree Synthesis) to meet the performance, yield and manufacturability targets. We show the development of the block from its previous generation floorplan to the latest generation and highlight the problems we encountered in floor-planning and placement as well as the solutions to these problems. Finally, we take a look at the changes to the CTS methodology which allowed us to meet the performance targets and increase the timing margins for better yield in all PVT corners.

Analog Net Routing with IC Compiler Custom Co-Design Flow
Johannes Brücker - Renesas Electronics Europe
Today's complex System-on-Chips (SoCs) are typically not limited to a lot of digital hard macros, but also have more and more mixed-signal and analog IPs. The majority of IPs have analog-nets with physical and/or electrical constraints, which can't be handled by a classical signal router.

Manual routing is very time consuming and error prone. Floor plan changes force a designer to start from scratch, which is not acceptable in a tight implementation schedule. On the other hand, all these constraints are well known in the analog design environment, so the solution is to combine both worlds to establish a seamless integration.

This paper describes the Synopsys ICC Custom Co-Design flow to allow the seamless data interfacing between digital and analog world, based on the common Milkyway database. In addition it illustrates how to perform interactive or automatic constraint driven analog-net pre-routing within Custom Designer and the interfacing back to the digital world.

Resolving the Double Trouble in 20nm Place and Route
Ulrich Hensel, Rainer Mann, Steffen Seeling - GLOBALFOUNDRIES, Jens Peters - Synopsys GmbH
In addition to Optical Proximity Correction (OPC) and Phase Shift Masks, 20nm BEOL requires double patterning techniques (DPT) for feature sizes smaller then 45nm half pitch using common 193 nm wavelength light source for Lithography. GLOBALFOUNDRIES has successfully deployed Synopsys ICC Place and Route to tape-out a sign-off clean and decomposable layout for its 20nm technology qualification test chip.

This paper describes specific aspects of the 20nm place and route flow that required attention during the enablement and testchip design work. These cover Milkyway technology file definition, standard cell library preparation, floorplannig, placement and routing.

A 20nm GLOBALFOUNDRIES ICC reference flow based on Synopsys ICC LCRM flow has captured the learning’s from this design process.

A3 - System Design - Architecture Analysis
Power Modelling of 3D-Stacked Memories with TLM2.0-based Virtual Platforms
Matthias Jung, Norbert Wehn, Christian Weis, Patrick Bertram - University of Kaiserslautern, Gunnar Braun - Synopsys GmbH
Three-dimensional stacked Wide I/O DRAMs have been proposed as a promising solution to overcome the pin-limited memory performance growth, the power vs. bandwidth dilemma and the Memory Wall. This new DRAM architecture and organisation requires a new generation of DRAM memory controllers. Virtual platforms enable us to explore the complete design space of memory controllers with an accurate power modelling at the system level with very fast simulation speeds and precise timing accuracy. In this paper, we present a virtual platform based on Synopsys Platform Architect for a fast and precise power estimation of multi-channel Wide I/O DRAMs.

High-Level Power Modeling with Synopsys Platform Architect - A Signal Processing Use-Case
Bernhard Fischer, Christian Cech - Siemens
In the era of ubiquitous cyber-physical systems and limited/costly energy resources, device power consumption has become a high priority – an adequate power modeling and analysis with high confidence level is a foundational part of a leading-edge system design flow. For short design cycles it is beneficial to apply a power modeling and analysis flow with sufficient accuracy, which is seamlessly integrated in early development stages. Power analysis can be done from high abstraction levels (functional level) down to abstractions closer to real-hardware implementations (gate level) where the modeling and simulation effort is usually very high.

In this paper we tackle the question of power modeling with a top-down approach, comparing a conventional spread-sheet-based high-level power estimation method with an ESL-based power analysis methodology supported by Synopsys Platform Architect.

Both power modeling and analysis methodolgies are presented in detail and their strengths and weaknesses, such as accuracy and modeling effort, are compared.

Low-Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs
Bart Vanthournout - Synopsys
When replacing fixed graphics hardware with a programmable embedded multicore GPU, or graphics processing unit, important questions remain: How many GPU cores? Which software mapping provides the best result? In this session we show how to use Synopsys Platform Architect to efficiently explore and optimize the HW-SW partitioning and mapping of a real-time video encoding algorithm onto an example multicore SoC architecture for both performance and power.

Target Audience: This session targets SoC architects working on multicore SoCs

A4 - Analog Mixed-Signal Verification
Enabling XA for Spectre-based Process Design Kits: a Look at Modeling Qualification
Simone Locci, Klaus-Willi Pieper - Infineon Technologies AG
The Synopsys tool XA offers several interesting features, its ability of performing fast SPICE simulations being the most relevant. To enable its use for existing Process Design Kits (PDKs) which are already developed around other simulation technologies, like Spectre from Cadence, the porting process to XA requires not only a translation of all involved model libraries, but also a thorough model qualification. It is fundamental that simulations carried out with one simulator perfectly correspond to those performed with the other one. In this paper, we would like to present how we qualified our technology libraries and how the cooperation with Synopsys led to the development of a new set of “Spectre flavored” compact model primitives for XA.

An Accurate Path Verification to Secure and to Speed up Nanometer Design Closure
Salvatore Santapà, Alessandro Valerio, Pierluigi Daglio - STMicroelectronics, Andrea Barletta - Politecnico of Milan, Massimo Prando - Synopsys
When designing high-performance ICs, it is often challenging to make out whether there is margin for improvements in solely relying upon information produced by STA. Furthermore, at sign-off you may wonder if some critical paths will eventually work, also in case of different adopted conditions.

This paper describes a validation flow able to provide a user-friendly Timing/Power-Path Calculation based on analog simulations and leveraging custom TCL procedures. The latter able to extract a back-annotated SPICE netlist from a PrimeTime run and launch CustomSim simulations in order to quickly obtain accurate data.

Such a timing analysis adds robustness to the design flow, thus allowing to explore design implementations and verification tasks not so easy to achieve in the frame of a pure digital flow: accurate skew measurements on wide busses, clock tree implementations driven by EMI criteria, design quotation in advanced and/or preliminary technologies, measurements outside the standard libraries domain characterization.

Circuit Check Extension to Optimize ERC Flow, User Experience and Guidelines for Expert and Novice Users
Alessandro Valerio, Salvatore Santapà, Pierluigi Daglio STMicroelectronics, Italy, Carlo Borromeo - Synopsys, Italy, Chi-Tzung Wang - Synopsys, Taiwan
Static ERC (Electrical Rule Check) verification allows design weaknesses to be found earlier in the development cycle, thus reducing the cost of fixing. Fast engine and efficient algorithms are key aspects for the deployment of this methodology. On one hand, the CCK built-in commands have better performances than a solution based on TCL-CCK electrical propagation but, on the other hand, they lack control capability for violation investigation. One of the latest enhancements implemented for "sdevv" breaks the rules and opens a new era in the static electrical verification: this solution builds a real bridge between the capacity of C-commands and the flexibility of custom TCL scripts. In the reporting stage of an ERC run, ad-hoc procedures query the design database in order to classify, tag or remove the current violations. Experiments on real IPs and SoCs have been carried out. Results prove how this new built-in check extension is overall more efficient than the old approach.

A5 - Digital Verification
Making the most of SystemVerilog and UVM: Hints and Tips for New Users
Dr. David Long - Doulos
In the two years since UVM 1.0 was released, Doulos has seen a big increase in customers wanting to learn SystemVerilog: UVM has become the standard verification environment for many companies. However, engineers often find that the size and complexity of the SystemVerilog language and the UVM class library make it hard to learn and make effective use of many features. This paper is intended to give guidance about useful features of both SystemVerilog and UVM that are often overlooked, used incorrectly or simply avoided because they are perceived as being "too hard." The first part identifies the most common novice-user mistakes and sets out rules to avoid them. The second part discusses useful enhancements to verification capabilities that can be obtained from deeper understanding of a few SystemVerilog and UVM features. It provides simple examples and guidelines to show how each enhancement can be achieved.

VCS Technologies for Best Debug and Analysis
Werner Kerscher - Synopsys
This tutorial will focus on several technologies recently added to VCS that dramatically improve debug productivity. Checkpoint and interactive rewind enable the user to quickly step back in simulation time without having to restart and rerun the simulation. Dumping and browsing of dynamic/testbench objects is now possible using the DVE Object browser which allows complex object relationships to be displayed. Recent improvements to the DVE Constraint GUI allow graphical constraint debug, what-if analysis and distribution-debug to be performed. Finally UVM and VMM specific debug topics will be covered.

Target Audience:
Verification Engineers and RTL Designers who want to debug SystemVerilog testbenches more effectively using the latest tools, tips and techniques.

A6 - Vision Session - High-Performance Core Implementation
Engineering Trade-Offs in the Implementation of a High-Performance ARM® Cortex™-A15 Dual Core Processor
Joe Walston - Synopsys, Inc.
Learn about the engineering trades-offs and flow development process to balance gigahertz+ performance and low power on a dual core ARM Cortex-A15 processor sub-system. This tutorial will show how to use engineering best practices and the Galaxy platform to meet challenging performance targets while maintaining leakage power in TSMC 28HPM design projects. Some key Galaxy features used include physical guidance for a predictable implementation flow, transparent interface optimization for top-level closure, and final stage leakage recovery for leakage power optimization. The techniques in this session can be used in your ARM Cortex-A15 implementations.

Target Audience:
Design implementation engineers working on ARM CPUs, GPUs, and other high performance cores

Design with FinFET
Marco Casale-Rossi - Synopsys
While planar CMOS devices have worked well down to 20 nanometers, FinFET devices do offer superior attributes and demonstrate much better results in terms of performance, static and dynamic power at 14 nanometers and beyond; however, although FinFET is considered as the most promising device for emerging technology nodes, it introduces new design complexity for electrical simulation, parasitic extraction, and IP development. Please, join this vision session to hear what EDA is doing to hide unnecessary details, whilst enabling designers to get the most out of this new, exciting technology.

Target Audience:
Design implementation engineers and managers interested in high performance designs and advanced process node developments and challenges

Tuesday, May 14, 2013
1:15 PM - 2:45 PM
B1 - Implementation - Low Power
Improved Methodology for Leakage Optimization in Synopsys Tools
Jürgen Karmann, Ravikumar Rajendraprasad - Infineon Technologies AG
Leakage power is a significant contributor to total power, which grows exponentially at high temperatures. A very effective measure to reduce leakage is to swap high-performance cells with low leakage cells, wherever timing closure allows. Design Compiler and IC-Compiler provides the cell sizing and cell swapping functionality along with the implementation flow to gain the power recovery. Implementation details are given to optimize various steps in Design Compiler and IC-Compiler. A new functionality in Primetime-ECO allows swapping cells on sign-off timing. The assessment of the different solutions showed that the amount of leakage power saved can be significantly improved by a proper methodology with reduced number of iterations. The new functionality of Primetime-ECO will be presented along with design implementation flow methodology. This article concludes with improved leakage optimization results and an overview on better tool runtime which has been observed.

Low-Power Verification using Power State Table Coverage
Christophe Lamard, Jean Marie Guillermin - ST Microelectronics, François Cerisier, Mathieu Maisonneuve - Test and Verification Solutions, France
This paper describes low power verification principles and the use of power state table to identify invalid power states and power transitions. The paper will show how to use the UPF power state tables to describe valid states and transitions for verification purposes. We will then explain issues related to reset states and transitional states and show how to use the power state table coverage to identify new sequences to implement.

Meeting Quality Goals for Gigascale Designs Trends and Solutions Part 1
Nikolaus Mittermaier - Synopsys
This tutorial will highlight leading-edge capabilities in the Synopsys' synthesis-based test solution for maximizing productivity, increasing test quality, and lowering test cost. We will discuss how standards-based DFT has evolved within DFTMAX compression to save time and effort implementing test for extremely complex designs. Next, we will examine several advanced detection mechanisms in TetraMAX ATPG for improving defect coverage. We will then show new features in the tools that lower the cost of testing ARM processor-based designs and other multicore SoCs.

Target Audience:
Test engineers working on ATPG and DFT and RTL-designers working with synthesis

B2 - Implementation - Signoff
Double Patterning. Something to Worry about in Parasitic Extraction?
Double Patterning has been introduced in 20nm technologies to overcome current lithography limitations and due to mask shift it creates additional variation in the parasitics of the interconnect system. There are different ways available of modeling this impact in Parasitic Extraction. In the paper we describe the spacing dependent permitivity model, discuss the modeling accuracy and compare it against other models using a simplified wire configuration. Based on a real design we demonstrate how to run PEX taking into account DP and review the results.

Static Noise Analysis Including Power Noise
Sönke Grimpen - Infineon
Voltage drops on power lines do not only affect timing, but also affect signal integrity. This noise on power lines is propagated via the driving transistor to the signal lines and potentially adds up with the signal noise. The paper discusses different approaches in creating a static model for a dynamic effect and their trade-offs and how to introduce it into PrimeTime.

Qualification of Setup/Hold Time Calculation in PT 2012.06 without Delta Transition
Sönke Grimpen - Infineon
PrimeTime SI 2012.06 release ignores delta delays when computing library setup and hold times, while previous versions took delta transition into account. This typically results in much smaller setup and hold times. The obvious question now is: is this optimistic and why not?

This paper discusses a principle approach in qualifying this new behaviour.

B3 - System Design - Virtual Prototyping
Introduction to Hybrid Protoyping
Philipp Jacobsohn - Synopsys GmbH
The presentation is intended as an introduction to the subject of Hybrid Prototyping, a combination of "Virtual Prototyping" (using abstract C models) and "Rapid Prototyping" (using RTL code running on FPGA-based prototyping boards). It discusses concepts, tools, and flows that allow both of the two prototyping concepts to communicate with each other. The presentation also provides information on how to decide which part of a complex system should be implemented "in hardware" or "software" and also shows information on the results that could be expected from running a "Hybrid Prototype".

Target Audience
Verification, Prototyping, Systems and FPGA Engineers

Next-Generation Prototyping - a Hybrid Approach
Peter Blöcher, Uwe Grüner - ST-Ericsson
HW/SW Co-Design, Verification and Validation of modern SoCs are challenging tasks. One approach is the use of modern FPGA prototyping systems, providing plenty of resources, in terms of logic gates, memory, even processors. Virtual Platforms are another way to go. C-models instead of RTL blocks and fast processor models allow to simulate the relevant parts of the SoC at a high-level.

The next and consequent step is the combination of the better of the two worlds: cycle-accurate and almost real-time speed of an FPGA-based prototype and the high-level modelling on a virtual platform of processors and hardware blocks not yet developed in RTL.

ST-Ericsson took the opportunity combining the Synopsys HAPS FPGA Prototyping Platform and ST-Ericsson’s in house Modem Virtual Platform with the use of Synopsys' set of AXI3 transactors. This paper explains the necessary steps, issues and challenges towards a unique Hybrid Prototyping System.

Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures
Srinivas Boppu, Vahid Lari, Frank Hannig, Jürgen Teich - University of Erlangen-Nuremberg
We present the prototyping of a heterogeneous multiprocessor system-on-chip (MPSoC) design, which consists of general purpose RISC processors as well as novel accelerators in form of tightly-coupled processor arrays (TCPA). In general, TCPAs are well suited to accelerate numerous compute-intensive tasks such as video and other digital signal processing.

We consider a transactor-based co-design approach where the TCPA is implemented on a CHIPit system and performs image processing of video data in real-time, whereas parts for control and configuration management of the MPSoC are realized in software on the host PC. For interaction between the two parts, the Synopsys Transactor Reference Library is used.

The design employs an AHB bus where some components are in the FPGA whereas other components are implemented in software and are communicating to the bus using AMBA transactors. This co-design approach significantly reduces design time when evaluating architecture alternatives.

B4 - Analog Mixed-Signal Verification
The Art of Reliability: Guidelines to Reduce IR-drop and Electro-migration Effects in Full Custom Designs
Paolo Valente, Alessandro Valerio - STMicroelectronics, Claudio Rallo - Synopsys
The design of power and signal nets are very strategic and sensitive in analog designs. The more complex the design is, the more challenging net design and more burdensome the verification. Considering the time necessary for parasitic extraction, verification and possible layout fixings, a dedicated flow is necessary and strategic. It would ensure not only a significant reduction in implementation phase but also a substantial turn-around time reduction of the overall IR-drop and electro-migration reliability checks.

This paper proposes guidelines for a flow-targeted design of analog nets and describes the new key features which have been implemented in Synopsys HSIMplus tool (current reuse, static analysis, missing VIA/strap check). The innovations described are related to different phases of the design: implementation, verification and script-based design modification. Finally, the results of the key features introduced are presented as well as the further possible enhancements of the flow.

The Synopsys IR-drop and electro-migration flow has been enhanced with new HSIMplus features, which have been requested and implemented to let other Synopsys users reduce the time necessary for design and verification of nets in analog design.

Transistor Level Static Circuit Analysis to Tackle ERC & ESD Challenges
Uwe Trautner - Synopsys GmbH
With semiconductors delivering faster speeds at reduced operating voltages, ERC (electrical rule check) to address issue such as power leakage is critical. A transistor level static circuit analysis solution, such as CircuitCheck, can apply circuit topology and connectivity to efficiently discover potential design errors that might be missed with traditional full-blown simulation methods. Join this tutorial to learn new ERC & ESD analysis approaches available in CircuitCheck and the advantages in coverage, capacity, and stimulus independence CircuitCheck provides. Discover how the transistor level static analysis, combined with Custom Explorer Ultra, can be used to visualize ERC/ESD violation and then conduct further circuit debugging.

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers

Analog and Mixed-signal Verification Methodology Using Verilog-AMS
Peter Thompson - Synopsys
The majority of today's designs contain significant analog and mixed-signal content. Even SoCs that are designed for essentially digital functions still require PLLs for timing control, digitally-controlled power management circuits, and high-speed I/O devices. In this tutorial we discuss how the Synopsys analog/digital co-simulation methodology can be used for logic and timing verification of mixed-signal designs that contain digital place-and-route, custom digital and analog circuits. We will discuss behavioral modeling techniques for improving simulation performance and enabling top-down design. This includes comparing Verilog-AMS with Real Number Modeling and creating different models for some mixed-signal blocks.

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers

B5 - New Technology - Verification Springsoft
Introduction to Verdi³ Automated Debug System
Jens Dickel - Synopsys GmbH
The Verdi3 Automated Debug System is an advanced open platform for debugging digital designs with powerful technology that helps you comprehend complex and unfamiliar design behavior, automate difficult and tedious debug processes and unify diverse and complicated design environments.

This tutorial provides an introduction of debug automation used to analyze results from implementation tools and for debugging simulation failure. You will also learn to build custom applications by using Verdi3's C and TCL-based programming interfaces and how to personalize Verdi3 to maximize your productivity.

Target Audience:
Verification Engineers, RTL Design Engineers, Design Implementation Engineers and SoC Engineers

Certitude and VCS at Module-level: a User's Experience
Stephanie Legeleux, Andreas Pachl, Rafael Pena Bello - Freescale Semiconductor
Certitude was acquired last year by Synopsys. What are the strengths and gotchas of this verification qualification tool? This presentation will go through application examples of Certitude on two block level testbenches, one focusing on directed stimulus while the other uses a random stimulus approach. It will highlight the differences in methodology applying Certitude for both of these testbenches, stress some critical points to understand about the tool operation as well as show examples of verification weaknesses found.

Get Certitude About Your Tapeout Quality
Joachim Geishauser, Alexander Schilling, Stephan Ruettiger - Freescale Halbleiter Deutschland GmbH
Functional bugs are still a major contributor to chip respins. One of the main issues that causes bugs to escape during functional verification is to determine the verification quality. One of the metrics used in the past was toggle coverage at the SoC level. However, this only gives an indication that something was completely missed in verification. The paper will show how the Synopsys Certitude tool can be used to improve the quality of the SoC verification as well as how the tool can be used effectively.

B6 - Vision Session: High-end Implementation Trends
Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor
Dale Lomelino - Synopsys, Inc.
Learn how to fit the highest possible performance within a tight power budget for a quad core ARM Cortex-A7 processor sub-system. This tutorial will highlight the latest technologies in Design Compiler Graphical and IC Compiler and how they can be used to achieve challenging power/performance targets in TSMC 28HPM. Low-power features of the Synopsys Reference Methodology for DCG & ICC optimization are supplemented with aggressive power management of the library VT classes and timing targets. Power is managed as the #1 requirement at each step in the flow, including synthesis, place_opt, clock_opt, route_opt, and focal_opt timing-closure. Additional power is recovered using Final Stage Leakage Recovery (FSLR), or "focal_opt -power." The techniques in this session can be leveraged for your ARM Cortex-A7 implementations.

Target Audience:
Design implementation engineers working on ARM CPUs, GPUs, and other low-power cores

Emerging Node Challenges and Opportunities
Thomas Andersen - Synopsys
Emerging nodes like 20nm present a unique set of challenges that the physical designers must mitigate. This talk will highlight how IC Compiler has emerged as the leading choice that has proven to overcome such challenges with a comprehensive solution that enables physical design and verification at these emergent challenging nodes.

Target Audience
Design implementation engineers and managers interested in high performance designs and advanced process node developments and challenges

Tuesday, May 14, 2013
3:15 PM - 4:45 PM
C1 - Implementation - Test
DFT and ATPG for Mixed 2-phase Latch and Edge Triggered Flop-based Designs
Richard Illman - Dialog Semiconductor
The use of both 2-phase clocked latches and edge triggered flops in scan based test poses a number of problems for scan insertion and test pattern generation; particularly when combined with scan compression. However, the use of these types of sequential elements is becoming increasingly important in low power applications. RS type latches are also needed to capture asynchronous events, but can cause DFT problems. This paper describes DFT styles and ATPG flows using TetraMAX and DFTMAX within the Synopsys environment for this design style. The topics covered include design and clocking rules, library models, DFT rule checking, ATPG and verification/debug. The paper also covers techniques to improve IDDQ/burn-in coverage for these design styles.

Meeting Quality Goals for Gigascale Designs: Trends and Solutions
Nikolaus Mittermaier - Synopsys GmbH
This tutorial will highlight leading-edge capabilities in the Synopsys' synthesis-based test solution for maximizing productivity, increasing test quality, and lowering test cost. We will discuss how standards-based DFT has evolved within DFTMAX compression to save time and effort implementing test for extremely complex designs. Next, we will examine several advanced detection mechanisms in TetraMAX ATPG for improving defect coverage. We will then show new features in the tools that lower the cost of testing ARM processor-based designs and other multicore SoCs.

Target Audience:
Test engineers working on ATPG and DFT and RTL-designers working with synthesis

C2 - Implementation - Advanced ICC Features and Methodologies
Clockgating and Concurrent Clock & Data Optimization in IC Compiler for Improved Timing Closure
Frank De Meersman - Synopsys
This tutorial introduces new ICC features targeting higher frequencies and improved ease of use. We’ll describe enhancements to the placement and optimization of the clockgating elements prior to CTS, which deliver improved timing and convergence of the flow. The new features use improved clockgate restructuring and CTS latency estimation for more accurate clockgate placement and clock enable path timing optimization. The session will also cover new skew features in IC Compiler which use techniques including multi-stage slack borrowing and on-the-fly clock tree adjustment. These features will enable you to meet frequency goals using a simple flow, without resorting to complex multipass approaches.

C3 - System Design - Prototyping & HLS
Model-based Design with Synphony MC High-Level Synthesis
Philipp Jacobsohn - Synopsys GmbH
Designers today need high-level synthesis optimization technologies that deliver high quality of results for FPGA and ASIC while enabling rapid exploration of performance, power, and area. The Synphony High-Level Synthesis (HLS) tool provides an efficient path from algorithm concept to silicon and enable greater design and verification productivity. Synphony Model Compiler provides an optimized implementation path from Simulink models and Matlab m-code into RTL. With Synphony, users can specify designs at a very high level of abstraction using IP model libraries, and then use the Synphony HLS compilers to create optimized RTL and testbenches for ASIC and FPGA, FPGA-based and virtual prototyping, and for verification using C or RTL.

Target Audience:
System engineers, algorithm designers, and RTL design engineers considering to adopt a high-level-synthesis approach

C4 - Full Custom Design
Moving from Virtuoso to Synopsys Custom Designer
Gernot Koch, Erich Gottlieb, Jonathan Bradford, Thomas Dilling, David Small - Micronas GmbH
In 2012, we decided to move our full-custom design environment to Synopsys Custom Designer. This paper describes our experiences and the work we had to do to make this move possible. This involved creating/porting multiple PDKs for our own wafer fab, porting ca. 80k lines of Skill customization code to Synopsys-TCL, and moving automotive project data with a 10+ year history into the Synopsys environment. We also share our experiences with the Synopsys environment so far, both positive and negative. These experiences include a number of fringe tools which have been switched or introduced as well (e.g. HSPICE, ICValidator).

Laker Custom Layout Solution: An Advanced Process Node Custom Layout Tutorial
Uri Golan - Synopsys Israel
In this technology session you will learn about the new layout challenges introduced by 20nm and below process technology. You’ll see basic SDL capabilities including hierarchical manipulations and layout reuse as well as the advanced features in the Laker Custom Layout Solution that help with these issues. Laker is extremely fast and has unique automation features that are ideal solutions for those seeking to improve layout productivity. Technologies that will be covered in this tutorial include Laker’s rule-based layout, schematic-driven layout, and pattern-based multi-device layout features – which have been all fully updated for process nodes at 20 nanometers and below.

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Layout Engineers.

C5 - IP - Implementation & Verification
High-Speed Interface IP Selection, Module Level, and Chip Top Level Verification
Andreas Vielhaber - Synopsys GmbH
Low-power, high-speed interfaces (like MIPI Interfaces utilizing MIPI MPYH or DPHY or USB SSIC utilizing MIPI MPHY) are required in today’s mobile device/platform to address the increased bandwidth needs. This paper addresses the complexity of design requirements and challenges to ensure Controller and PHY interoperability and related verification by the example of USB SSIC. We will further discuss top level verification and its reuse of existing test cases.

FPGA-based Emulation of an Ultra Low-Power SoC
Martin Gut - Texas Instruments
Nowadays there is a fast-paced need of new less-power demanding products. Technologies as power domains result in extremely complex clocks trees and many multiple possible power states. In addition, SoC embedded applications are bringing important new challenges to the verification engineers. This paper illustrates TI's FPGA-based emulation methodology for RTL verification, hardware and software co-verification and sign-off of an ultra-low power SoC.

Comprehensive System Validation of an Ultra-Low Power SoC with an FPGA-Based Emulation System
Martin Gut - Texas Instruments, Laureano Carrasco - Synopsys
Nowadays there is a fast-paced need of new less-power demanding products. Technologies as power domains result in extremely complex clocks trees and many multiple possible power states. In addition, SoC embedded applications are bringing important new challenges to the verification engineers. This demo illustrates TI's FPGA-based emulation methodology for RTL verification, hardware and software co-verification and sign-off of an ultra-low power SoC.

C6 - Design Flow - Lynx Design System
Using the Lynx Design System to Minimize the SoC Implementation Effort and Cost
Simone Borri, Pierre-Marie Signe, Christian Eichrodt - Abilis Systems, Riccardo Giordani - Synopsys GmbH
Competitive performance and schedule pressures often drive semiconductor companies to migrate to smaller technology nodes.

These migrations are usually expensive in terms of time and resources and pose risks to critical projects because they require specialized skills and flow development in parallel with chip development.

In this paper, we will take you through the process of migrating to full Synopsys-based RTL-to-GDSII flow from the prospective of a company focused on controlling design costs, evaluating different process technologies, quickly integrating third-party IP, getting to a stable flow deployed to the design team as quickly as possible, and maximizing the performance of the design.

We will discuss the key aspects of Lynx that allowed us to achieve our goals on a recent digital TV chip project, including the integration of analog tools such as Custom Designer into the flow.

Improve Design Quality with Efficient Design Exploration in Lynx Design System
Riccardo Giordani, Chris Smith - Synopsys
Today's SoC designs require unique implementation tradeoffs between power, performance and area to achieve the best results for a specific application while keeping to a tight design schedule.

The solution space for finding optimal results is very large and involves multiple variables and without sufficient exploration of alternatives the optimal and most efficient implementation may be missed. In addition. late design cycle changes such as timing ECO's often require assessment of multiple possible strategies.

Target Audience:
Front-end and back-end design engineers, CAD engineers, flow developers and project leads