|Wednesday, May 23, 2012|
10:45 AM - 12:15 PM
|A1 - User & Tutorial Session: Digital Implementation - Low Power|
|Clock Gating Analysis in Primetime-PX to Optimize Clock Gating Efficiency|
Juergen Karmann, Joachim Voges - Infineon Technologies AG
Clock networks consume a significant amount of dynamic power in today's designs. Whereas clock gating is the most efficient measure for clock power saving. Local clock gating is facilitated by proper RTL code and implemented by Power Compiler during logic synthesis. This paper discusses the capabilities of Power Compiler on VHDL examples and presents a flow based on Primetime-PX to analyze the RTL code for clock gating potential. Clock gate efficiency and toggle rates at the CP and Q pins of the registers are applied to identify clock gating opportunities. Register power is used to quantify power saving. The presented flow can be deployed at any post-synthesis stage of the design. A proper activity pattern is mandatory, which can be provided as RTL-VCD during development or as gate level VCD in the sign-off phase. The presented methodology is illustrated by an example of customized PT-PX reports, which enables systematic clock activity assessment.
|Introduction to IEEE1801 (UPF) Supply Sets|
Knut Dalkowski - Synopsys GmbH
This tutorial will help attendees to decide on the right time to move to the new IEEE1801 syntax of Supply Sets. After comparing Supply Sets to the traditional syntax of UPF1.0 Supply Nets, the implications of the new UPF coding style are discussed. Re-Use of IP blocks can be enhanced with Supply Sets by abstracting the Supply Nets used in backend implementation. New isolation syntax takes into account source and sink supplies, which helps to remove isolation redundancy and increases UPF coding productivity. Explicit and implicit Supply Sets are compared, trading off UPF code size with verboseness of the specification.
Target audience: Digital designers- frontend or backend. Designers working on advanced nodes. Designers working on Low Power designs.
|UPF 2.0: Expectations and Experiences|
Peter Kamphuis, Guido Schlothane - Intel Mobile Communications
Unified Power Format, as originally introduced by Accellera, meanwhile is an established quasi-standard enabling a common power-aware implementation and verification flow for semicustom digital designs.
The extended capabilities of UPF 2.0, also known as the IEEE 1801-2009 standard, are expected to leverage productivity and to improve robustness of designs. This paper will give first-hand experiences and shows which expectations can be fulfilled.
|A2 - User Session & Demo: Digital Implementation - Design Exploration and Feasibility|
|DC Explorer - Fast Synthesis for Early Design Exploration|
Herbert Taucher, Andras Rappai - Siemens AG ; Rolf Ferner - Synopsys
Implementing SoCs with complexities of far more than 100 million gates in leading edge technologies bring up a new class of challenges. Although the tools for verification and synthesis become faster with every release, the ever increasing turn around times for synthesis caused by this complexity do no longer allow to run multiple synthesis trials to get results as quick as possible, in order to explore different RTL coding, constraints, and floor planning.
To benchmark different design variations, we evaluated “DC Explorer” which claims not only to run faster than "DC-Ultra", but also handles incomplete design data, and delivers a 10% timing and area correlation to “DC-Ultra”. We tested "DC Explorer" on two blocks from our actual signal processing SoC project and will share the correlation of results as well as the impact on design flow and design productivity.
|Test your Chip with your PC; Running tests, as easy as browsing the internet with your computer|
Frank Nolting - Synopsys GmbH
This demonstration will feature the STAR Memory System on a single test chip - accessed through IEEE 1149.1 (JTAG) via a USB connection from a laptop. The test device is driven by a production software component of the STAR Memory System called Silicon Browser, which can be used for post silicon debug and repair of embedded SMS BISTed memories. The Silicon Browser basic driver and pattern generation features can demonstrate some successful memory BIST runs.
Target audience: Test engineers and managers.
|Hippo Lake: A case Study of Automated Design Planning in High Speed Designs|
Justin Barber, Victoria Kolesov , Michael McCoy, Atul Walimbe - Intel
Automated design planning solutions bring efficiency to full chip floorplanning, assembly, and integration. High speed designs represent a unique set of challenges: Stringent timing, power and quality specs require many iterations for fine grained optimization, including hand-crafted optimal port placements, routing topologies, and buffering solutions. Can automated design planning tools achieve a similar level of TAT here as ASIC design without compromising on frequency, power and quality? We examine how the latest advances in EDA capabilities such a x-boundary timing optimization, relative placement for block/top level co-design, etc can be used to implement a production high speed CPU design.
|A3 - User Session: Digital Verification - Testbench Methodology and Debugging|
|I Spy with My VPI: Monitoring Signals by Name, for the UVM Register Package and More|
Jonathan Bromley - Verilab
Verification environments commonly need to react to value-changes on arbitrary DUT signals that are not part of a standard interface protocol. The package presented here supports both value probing and value-change detection for signals identified at runtime by their hierarchy name, represented as a string. This provides a useful enhancement to the UVM Register package, allowing the same string used for backdoor register access to be used also for value-change detection. It is also an interesting case study in the use of SystemVerilog DPI and VPI in the same package. For environments entirely coded in SystemVerilog, the package is completely portable. We also discuss how it can be applied to VHDL signals in a mixed-language environment. The package source code will be freely available under the Apache 2.0 licence.
|How to Improve Verification Debugging using DVE|
Joachim Geishauser - Freescale
Today’s designs and therefore also the testbenches become more complex. The time spent to de-bug testbench and design issues is very long. The paper shows how the Synopsys transaction recording built into VCS® and Discovery Visualization Environment (DVE) can be used in SytemVerilog (SV) testbenches. The paper will also outline an enhanced concept on how to extend the signal based trace driver concept beyond the design border into the testbench transaction level traces.
|A Guide to Using SystemC TLM-2.0 IP with UVM|
John Aynsley, David Long, Doug Smith - Doulos
UVM 1.x includes support for the communication interfaces defined by the SystemC TLM-2.0 standard, although some implementation details differ. This enables integration of SystemC TLM-2.0 IP into a SystemVerilog UVM verification environment. The connection between SystemC and SystemVerilog currently requires a tool-specific language interface such as Synopsys TLI, since it is not yet implemented as part of UVM. This paper begins with a brief overview of TLM-2.0 aimed at novice users. It then discusses the steps required to add a SystemC TLM-2.0 model into a SystemVerilog UVM environment and simulate it with VCS. At each step, issues that users will face are explored and suggestions made for practical fixes, showing the relevant pieces of code. Finally, the paper gives a summary of areas where the UVM implementation of TLM-2.0 differs from the SystemC standard and proposes workarounds to ensure correct communication between the SystemVerilog and SystemC domains.
|A4 - User & Tutorial Session: AMS Verification|
|A Statistical MOSFET Aging Model for Monte Carlo Simulations with Hspice|
Florian R. Chouard, Stefan Drapatz, Christoph Werner, Cenk Yilmaz, Doris Schmitt-Landsiedel - Technical University Munich
In this work a physics-based reliability model has been developed for the NBTI effect in nanometer MOSFETs. It is based on state-of-the-art model equations for the trapping and detrapping of charges in the gate dielectric. We have applied it for statistical Monte Carlo simulations with HSPICE of SRAM-cells and Flip-flops.
|How to Get the Most from Your Circuit Simulation|
Uwe Trautner - Synopsys GmbH
Do you ever
• Wonder what the latest news is for Synopsys Custom and AMS solution?
• Wish you had insight into the latest advances in HSPICE & CustomSim solutions?
• Want to know how to get the best performance out of your circuit simulator?
This tutorial provides useful tips and tricks to reduce simulation time without compromising accuracy. Starting with HSPICE, the tutorial will cover tuning for better performance using the Runlvl command, convergence, RC reduction and other good practices. Then, for CustomSim (XA), we’ll reveal performance and ease of use enhancements targeted for simulation of memory designs.
Target audience: Analog/mixed-signal design engineers, CAD managers & engineering managers
|A5 - User & Tutorial Session: Physical Signoff|
|StarRC Accuracy Analysis of RC Extraction for Advanced Nodes (28nm)|
Hendrik Mau - GLOBALFOUNDRIES
Abstract-Interconnect parasitics are dominating the delay at advanced nodes below 90nm and 3d effects are impacting the accuracy of rule based 2.5d parasitic extraction. Due to this it is imperative to monitor the accuracy of the parasitic extraction carefully. We describe a method of accuracy analysis and filtering of results. The applied accuracy limits and test cases are listed.
|Parasitic Extraction for Emerging Technologies: Double-Patterning Aware Extraction and Timing Signoff at 20nm|
Clayton McDonald - Synopsys Sarl
Double patterning technology (DPT) has become an impending reality at advanced 20-nm and below process nodes. DPT provides an attractive alternative to more expensive lithography options, but it introduces new challenges in parasitic extraction and timing signoff analysis due to increased variation. This tutorial provides an overview of the double patterning technology and discusses StarRC’s latest parasitic modeling and extraction features to help designers signoff their 20-nm designs with increased confidence as before.
Target audience: Custom/analog/mixed-signal designers. Designers working on advanced nodes
|Parasitic Extraction for Emerging Technologies: Dealing with Metal Fill in 28nm ECO Extraction Flow|
Clayton McDonald - Synopsys Sarl
Design teams are facing increased schedule and tapeout pressures due to the increasing ECO time to close their complex system-on-chip designs. The situation is exacerbated at 28-nm as metal fill insertion has become a must-have step in IC design. Designers use physical verification tools to insert sign-off metal fill. Metal fill insertion and post metal fill extraction runtimes are critically important in overall ECO turnaround-time (TAT) and reducing them can accelerate the signoff analysis. This tutorial discusses new ways to reduce metal fill insertion run time and metal fill handling in StarRC to significantly improve ECO TAT.
Target audience: Custom/analog/mixed-signal designers. Designers working on advanced nodes
|A6 - User & Keynote Session: Automotive & Systems - Keynote & Virtual Prototyping|
|Automotive Track Keynote: Trends and Challenges in Automotive Applications Driving Development|
Dr. Ing. Christian Sebeke - RobertBosch GmbH
Modern cars represent a complex system comprising analogue/radio frequency (RF), passive, high-voltage (HV) power, sensor/actuator and micro-electro-mechanical system (MEMS) in addition to pure CMOS. We will look at application trends driving Tier 1 and 2 hardware development and set demand for further enhancement of EDA.
|Automotive System Verification using Saber/Modelsim Cosimulation in Conjunction with ISO 26262|
Bernhard von Edlinger, Josef Schmid – iSyst Intelligente Systeme GmbH, Andreas Plange- Conti Temic Microelectronic GmbH, Frank Lehmann –Synopsys GmbH
The increasing complexity in combination with the functional safety requirements according to IEC 61508 and ISO 26262 is a challenging task for engineers in the automotive industry. Not only the safety functions/applications themselves but also the supporting design process and tool chain have to be adapted according to the growing needs. Holistic system simulations with SPICE, MAST, VHDL and VHDL_AMS Models are required to verify the functional and safety behavior of the ASICs and modules including external circuits. With script-based automation we support the consistency, reproducibility and traceability requirements according to the mentioned standards. Especially the environment and configurations for different abstraction levels and re-use of design data/models with Saber/ModelSim co-simulations are handled by scripting and VHDL FileIO features. The requirements, specification and design data is verified by TCL scripts accordingly. Simulations, measurements, worst case analysis (WCA) and pre/post processing are controlled by TCL/AIM scripts for re-use, traceability and supporting review items.
|Applications and Requirements of Virtual Platforms in the Automotive Domain|
Ingo Feldner - Robert Bosch GmbH
While "hard" automotive applications have much in common with consumer electronics, the differences w.r.t. technical characteristics and constraints, development processes, and supply chains have to be taken into account before transferring methodologies to this domain.
Based on selected use-cases at Corporate Research and in the automotive Business Units we derive special requirements on using virtual platforms. Interoperability, Standardization and availability of models play a key role in the acceptance of this new methodology. We will point out how existing standards like SystemC and TLM 2.0 satisfy this need and what we think is needed beyond this.
Due to the heterogeneity of the embedded use-cases the tool environment for simulating such complex systems must assist the user of these platforms with all means needed to assemble and simulate a complete system. This includes that certain degrees of freedom must be maintained in order to tailor a platform to the users’ special needs e.g. coupling to existing simulators and tools.
The challenge in this area is to provide cost efficient models that can easily be adapted to the vast heterogeneity of use-cases.
|Wednesday, May 23, 2012|
1:30 PM - 3:00 PM
|B1 - User Session: Digital Implementation - Design for Test|
|Low Power Design Flow using UPF/CPF|
Markus Lanz - Austriamicrosystems
The paper shows how the power-intent language UPF is used in a power-sensitive battery-operated ASIC to implement the advanced power management techniques multi-supply voltage and power shut-off in simulation, synthesis and layout. It includes how to define the nine individual power shut-off domains, one operated at a lower voltage. The always-on power domain, containing the power management unit, had to be mapped to a low leakage library in order to meet the leakage power budget. The power switches are located in the analog part of the design. Cells like level-shifters and isolations cells are necessary in the standard cell library to run the automated design flow. Despite the fact that the UPF had to be translated to CPF for P&R and LEC the flow worked out quite well.
|The Application of DFT-Compilers Core Wrapper Technology to Control a Digital to Analog Interface|
Karl-Heinz Grieshober, Rainer Kropf, Gerhard Roither - Micronas New Technologies; Hans-Ulrich Grubert, Nikolaus Mittermaier, Frank Nolting - Synopsys
It is a common issue of mixed signal designs to control the digital to analog interface during test. This paper describes the automatic insertion of a core wrapper chain to fulfill the following tasks: during Intest mode shift-in stimuli to the input wrapper registers and apply dedicated safe values to all analog outputs of the digital block; during Extest mode enable tracing of the analog signals at the inputs and stimulating the analog outputs of the digital block. Detailed commands from the DFT insertion script are shown and tips and tricks are given to reduce the area overhead and the power consumption.
|DFT for Fragmented Digital Blocks in Mixed Signal Designs|
Richard Illman - Dialog Semiconductor
Increasingly mixed-signal designs have small digital blocks embedded within the analogue functions as well as a main digital core. This paper describes a scan compression architecture to minimise the impact and risks associated with this design style. It also describes the techniques used to ensure the accuracy of test coverage reporting in these types of designs.
|B2 - User Session: Digital Implementation - Hierarchical ICC and Constraining|
|Best Practices of Hierarchical Design Implementation Strategies|
Norbert Mueller - LSI
How to improve ASIC implementation TAT for complex designs?
This paper shows best practices of hierarchical design planning and implementation strategies. It covers hierarchical block handling through the implementation process including RTL, partitioning and floorplanning. Thereby it focuses on timing closure aspects such as hierarchical timing modeling and constraining timing by utilizing scenarios and modes.
|STA in Custom Design|
Andreas Küsel - Infineon
Most customs designs are verified by spice simulations only. We at Infineon believe that this is not enough. At least every digital synchronous path must be additionally timing verified exhaustively with a Static Timing Analysis (STA) tool. In this paper some limits of simulation based circuit verification will be highlighted and it will be explained why STA does not phase this issues. Even though custom designs are often not intended to be verified by STA it can mostly be done. Some data preparation as well as verification aware design partitioning is helpful and will be described. Additionally some pitfalls which should be avoided in layout as well as in schematic will be highlighted. In the end you will learn why this whole effort does not only give a higher confidence level at tape-out, but also reduces the characterization effort dramatically.
|Efficient Common Derating for Synopsys Implementation Tools|
Sönke Grimpen - Infineon Technologies AG
The ability to describe a fine grained derating concept taking into account logical depth, distance and supply voltage per library cell or even instance plus some guardband leads to a highly complex derating scheme. Goal of the “common derating” project within Infineon was to find a de-rating concept for Design Compiler, IC Compiler and PrimeTime describing different derating strategies based on a common data base. It should handle OCV and AOCV, derating of cell de-lays, interconnect delays and timing checks including flexible guardbands.
On our way, we discovered a number of traps and pitfalls. This is their story.
|B3 - Tutorial: Digital Verification - Verification IP|
|Discovery VIP - Overview and introduction to the next generation Verification IPs.|
Fabian Delguste, Adiel Khan - Synopsys
The role of Verification IPs is becoming even more important in current designs. This tutorial will introduce the next generation “Discovery Verification IP”. You will learn about the high performance architecture, the ease of use and the Protocol Analyzer which is key in debugging. The second part of the tutorial will show examples where the AMBA AXI4 and the Ethernet VIPs are used in UVM based testbench environments.
Target audience: Verification engineers. Designers verifying complex designs with lots of reuse and IP
|B4 - User Session: AMS Verification & Design|
|XA/VCS Powerup Simulation of Automotive SOC|
Roland Lengfeldner - Infineon Technologies Austria
This paper gives an overview about the usage of the XA/VCSMX co-simulator for the powerup simulation of the new generation Automotive SoC at Infineon. Main toplevel verification is based on pure digital simulations with real port VHDL models for analog blocks. This is done due to simulation runtime and setup complexity reasons. To cover simulation gaps, a transistor level simulation consisting of all relevant power supply blocks together with VHDL RTL code of the digital part has been setup. In order to increase simulation coverage, several possibilities have been implemented to speed up simulation time with a predefined and accepted loss of accuracy, e.g. to use simplified spice models for voltage generators. Further important topics, such as the setup of save operating area checks and automatic result checking using VEC files are briefly described at the end of the paper.
|An Optimized Sizing Procedure for Boost Converter Design|
Jan Michal - Certicon
In DC-DC power converter IC design, the sizing of the end stage power switch MOSFETs and their drivers is critical to achieving an optimum solution for a reasonable tradeoff between power efficiency and silicon area, as chosen by the designer. In the present paper, two basic types of approaches to solving the sizing problem used in a past project will be presented: (A) a novel simplified (semi)automated iterative approach based on the custom Designer's Simulation Outputs List window for a quick first approximate solution, and (B) a fully automated tcl-script based optimization method providing the ultimate solution of the related constrained-optimizaton problem. Both (A) and (B) methods use short spice transient analysis simulation runs of about 2 switching cycles. The circuit's duty cycle and inductor initial current are tuned by yet another short tcl script iterating these short spice runs to achieve steady state.
|Deployment of Full Custom Created Timing Shell Methodology to Hand off Macros from CD to ICC|
Michael Wagner; Oliver Baer, Kurt Haun - Synopsys
This paper shows a useful methodology to check timing through the interfaces from top-level SoC to the macros, and how we used Synopsys' ICC-Bridge as the Golden Gate from full-custom to the semi-custom world. It describes different design phases, gives an overview of the transferred designs, the used flow and the bottlenecks we had to find workarounds for.
|B5 - User & Tutorial Session: System - Designing Programmable HW|
|A Scalable Multi-Core ASIP Platform for Standard-Compliant Trellis Decoding|
Christian Brehm, Matthias Jung, Norbert Wehn - University of Kaiserslautern
Multi standard wireless modems are becoming more and more important in industry. The recent move to LTE will aggravate this issue. We present a scalable Multi-Core ASIP virtual plat form for trellis based channel decoding in multi-standard wireless modems. The basic building block of the platform is a weakly programmable IP-Core which was designed with the Processor Designer from Synopsys. This core has an implementation efficiency comparable to one of a dedicated architecture, however offers much more flexibility and supports convolutional and turbo code decoding for standards like GSM, EDGE, WiMax, CDMA2000, and LTE. The core was implemented in 90nm and 65nm respectively and is already in use in a commercial product. For a convenient design space exploration and scalability analysis, the multi- core architecture is modeled with Synopsys Platform Architect.
|Designing Programmable Hardware Accelerators: Gaining Flexibility Without Compromising Power, Area and Performance|
Gunnar Braun - Synopsys GmbH
Dealing with change has become more important than ever—whether you need to support a new emerging standard or respond to new functionality that your competition just released. So what about trading fixed hardware implementations for a programmable hardware accelerator? Is it possible to design such a programmable hardware that is flexible enough to deal with multiple standards and different use cases, while meeting power, performance and area constraints?
In this session we will cover how Synopsys Processor Designer allows hardware designers to efficently design and verify programmable hardware, covering the creation of optimized RTL code, software tools such as assembler, linker, compiler and instruction-set simulator as well as a SystemC model from a single formal input specification.
Target audience: Intermediate; design engineers, engineering managers, chip architects.
|B6 - User Session: Automotive & Systems - Saber|
|A Complex Glow Plug Interface Suitable for Monte Carlo Analysis with Saber Simulator|
Octavian Luca, Michael Decker – Continental Corporation
This paper describes an implemented model for multi domain simulation of Input Output Software, electronic components and thermal subsystems for semiconductors package and cooling heat sink. The passive and semiconductor components are modeled and parameterized according to device datasheet and include tolerances and temperature dependant behavior.
|Development of an Electrical Motor Control Based on a VSP|
Jens Harnisch, Albrecht Mayer, Dian Nugraha, Radovan Vuletic - Infineon Technologies AG
This presentation shows how a VSP with a microcontroller model was used to develop and refine an electrical engine control. The main motivation for using the VSP was the fact that with a pure hardware based development some electrical PCB components were frequently fused, when trying to tune the control algorithm. The contribution will present requirements for such a system simulation, also with regards to coupling to other tools, the simulation setup and major learnings.
|Accelerating the Development & Analysis of Automotive Systems through a Fully Automated Simulation-Based Approach|
Isabelle Maffat, PSA
Today, electrical and electronic simulations at PSA are mainly done in SABER. They aim to conceive, check and validate the electrical architecture, for each possible life situation of a vehicle. Thus, several constraints such as the kind of vehicle, the destination country, driving conditions, must be taken into account for the simulations. Standard method of simulation in Saber permits to cover a certain range of profiles, but isn't sufficient to respond to all needs in terms of simulations. The powerful pre/post processing possibilities in Saber, based on tcl/tk language, permitted to develop a specific module interfaced with a PSA Excel database, allowing parameterization and run of a large range of simulations. Consequently, PSA benefits from high gains in terms of quality, efficiency and cost.
|Wednesday, May 23, 2012|
3:15 PM - 4:45 PM
|C1 - User & Tutorial Session: Digital Implementation - Asynchronous Constraining & Datapath Implementation|
|An all-Inclusive Clock Domain Crossing Solution|
Charles Laurent, Phuong Nguyen, Joseph Dekoker, Domenique Spagnuolo - Sigma Designs
Asynchronous Clock Domain Crossings (CDCs) should always be carefully designed, especially at GHz speeds. This problem has been discussed in many papers but none of them have considered all of the aspects of CDCs - for example synthesis constraints are seldom mentioned. We will point out the potential issues of CDCs without carefully constructed synthesis constraints. In this paper, we present an all-inclusive solution for this problem - from design to synthesis and static timing analysis (STA) constraints. The solution is based on two elementary designs, one for control signals and the other for data path signals. Known problems for CDCs such as metastability, glitch, reconvergence, and timing constraints for a data path are solved by cell choice, synthesis and STA constraints. We will also show how to construct a CDC handshaking mechanism from these two elements as an example of implementation.
|Getting the Most from Synthesis to Improve Your Datapath QoR|
Reto Zimmermann – Synopsys Switzerland
With datapath content increasing in today’s designs, it is more important than ever to understand how to take advantage of the advanced datapath features in your implementation flow. This session will review recent and upcoming updates to the DesignWare Datapath IP that can help you achieve the QoR goals in your design. New features including internal rounding in the top down compile flow and datapath extraction analysis capabilities will be the focus of this presentation. Additionally, a brief refresher of the datapath RTL coding guidelines will also be presented.
Target audience: Intermediate; design engineers, engineering managers, chip architects
|C2 - User & Demo Session: Digital Implementation - Advanced Constraining|
|A Way To Future Sign-off: Hierarchical STA Using HyperScale|
Jürgen Dirks - LSI
Ever growing designs require tools and methodologies, which scale with these complexities. HyperScale offers a way out of the currently used full flat static timing verification for signoff. The present paper introduces this technology as a new modeling approach working within PrimeTime. HyperScale makes use of the hierarchical nature of highly complex integrated circuits by automatically re-using the block-level timing at the top-level. This allows for a reduction in IC development turn around times and simplifies hierarchical sign-off. An overview of the tool flow is presented and real-life design data is used to explain background and benefits as well as to perform comparisons to traditional signoff methods.
|Resolution of Common Constraining Issues - Galaxy Constraint Analyzer Demo|
Gernot Gall - Synopsys GmbH
This tutorial shows common constraining issues in complex designs, provides detailed explanations of the underlying problems and shows how to debug these issues with Galaxy Constraint Analyzer during a live session. In addition it will provide cross-references between GCA rule violations and the corresponding PrimeTime error/warning messages.
Target audience: Design and verification engineers involved in constraining and signoff
|C3 - User & Tutorial Session: Digital Verification - UVM and X-Propagation|
|Easier RAL - All You Need to Know About the UVM Register Abstraction Layer|
Doug Smith - Doulos
UVM provides the framework to create verification register models using the UVM Register Layer. While neither difficult to understand nor create, describing a register model can be quite tedious and rather burdensome to maintain. Hence the need for an easier UVM Register Layer, i.e. the quintessential elements of UVM Register Layer to practically get the job done right. In this paper, the UVM Register Layer concepts like register blocks, address maps, adaptors, predictors, front-door/backdoor access, built-in sequences, and coverage models are explained.
However, what truly makes for an easier register layer is the use of a register generator, which handles the tedious and hard work automatically. As examples, free generators like ralgen are discussed. Using register generators to build and maintain the register model, coupled together with some simple guidelines for integration, provides the essential knowhow to quickly and effectively benefit from using UVM’s Register Layer.
|Getting X Propagation under Control|
Werner Kerscher - Synopsys GmbH
The X-optimism semantics of standard RTL simulation can lead to incorrect behavior which often conceals design bugs. These bugs lead to passing simulations and creating problems that are difficult to correct later in the flow.
This tutorial explores a new method to address this problem that changes the X semantics in order to remove the incorrect results dues to X-optimism.
Target audience: Design & verification engineers and managers
|C4 - Tutorial: AMS - CD-ICC Co-Design|
|IC Compiler Custom Co-Design|
Oliver Bär - Synopsys GmbH
In attending this tutorial you will learn how the IC Compiler Custom Co-Design solution enables design teams to easily move between digital and custom implementation flows, while maintaining design data integrity. The unified solution accelerates the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development, including the time-critical tape-out phase. See how Galaxy Custom Designer, with tight integration to IC Compiler, enables higher productivity through advanced features such as DRC/LVS correct interactive mixed-signal auto-routing and DRC-aware custom editing.
Target audience: Custom/analog/mixed-signal designers. Designers working on advanced nodes
|C5 - Tutorial: IP - Memories and Libraries|
|Best Practices for Implementing Memories and Libraries to Deliver Superior PPA and Embedded Test & Repair|
Zaka Bhatti - Synopsys
Selection of memory compilers and logic libraries has significant impact on the power, performance and area of SoC designs. This tutorial presents best practices for implementing the optimal combination of memories, libraries and embedded test and repair to meet your design requirements. Also learn how the DesignWare Memory Compilers and Logic Libraries are used in conjunction with Synopsys tools, including ICC and DC, to deliver a high-performance, low-power and differentiated SoC design. Benchmarks on CPU and GPU implementations will also be shared.
Target audience: Intermediate; Design engineers, system architects
|C6 - User & Tutorial Session: Automotive & Systems - Linking Virtual Platforms and Saber|
|Virtual Platform for Profinet 2.3 Systems|
Karl-Theo Kremer, Claudia Kühn, Kai Liu, Andreas von Schwerin - Siemens AG
The present work describes the application of Virtual platform (VP) methodology for the development of the new version V2.3 of PROFINET (PN), a real time capable Industrial Ethernet standard. The heart of the PN devices is the PN-module, which provides all hardware functionality needed for PN V2.3. Modeling of this module was done in-house based on the SystemC Modeling Language (SCML). Modeling of some of the peripherals and initial build-up of the VP were done by Synopsys Professional Services. The Virtualizer Tool suite of Synopsys is used for building and running the VP.
The VP of a full PN-system is built by connecting the SystemC-ports, which correspond to the Ethernet ports of the devices, by a properly configured SystemC channel, representing the Ethernet cable between the devices. By this, basic communication network topologies like line, comb, or redundant ring are built in the VP and PN protocol traffic with optional error injection is simulated and proper system functionality is validated.
|Achieving Accurate & Fast-Paced Simulation for Automotive Power Semiconductors using the Saber/TCAD Integration|
Andre Jennert - Synopsys GmbH
Accurate power device models for H/EV design and verification are key to extending range and ensuring robust performance. This tutorial presents the latest developments in automated power device model generation linking Synopsys' TCAD device simulation and system-level Saber tools.
Target audience: H/EV power system design engineers, power electronics designer/validation engineers & managers
|Linking Saber & Virtualizer for Automotive Hardware/Software Co-Verification|
Lee Johnson - Synopsys Inc.
Extending beyond traditional Hardware-in-the-Loop testing approaches for automotive embedded system development, capabilities for Virtual Hardware-in-the-Loop (V-HiL) allow for testing earlier in the development cycle, increasing testing coverage and lowering testing costs. This tutorial introduces the concept of Virtual Hardware-in-the-Loop and highlights the linkage between Synopsys' Virtualizer and Saber tools for simulating the ECU in connection with a high-fidelity physical system.
Target audience: Engineers & managers involved in the design, validation, and calibration of embedded SW for automotive systems.
|CTMesh Or CTS|
Loh Phooi Choong, Ang Boon Chong, [Intel]
CTS or CTMesh is always a challenging choice to decide during PnR implementation. The intend of this paper is to study the comparison of CTS as well as CTMesh implementation in terms of latency, skew, power as well as routability trade off of both implementation.