|Thursday, May 19, 2011|
10:30 AM - 12:00 PM
|A1 Tutorial & User Paper - Implementation: Synthesis|
|DesignWare minPower Components|
Michael Confal [Synopsys GmbH]
To support higher data rates and provide a better consumer experience, designers need to incorporate more complex signal processing and multimedia content into their advanced SoCs. Because of the increased datapath content, design engineers have started exploring new design techniques to reduce the power consumption in datapath intensive designs. In this session, we will introduce how DesignWare minPower Components help solve these challenges. We will detail techniques to identify designs that will benefit from DesignWare minPower technology and the best practices for getting optimal results. This session also includes technology updates in recent releases.
Target audience: Intermediate; Design engineers, engineering managers, chip architects.
|Multi-Mode Multi-Corner Synthesis in Design Compiler - A Must or just Nice to Have?|
Bernhard Riess [Infineon Technologies AG]
The traditional design flow uses a common constraining – typically named umbrella constraining – for design implementation, while in the final timing sign-off the design is verified in every individual mode and corner of operation. Later on, multi-corner multi-mode (MCMM) was made available and applied in IC Compiler®. Since the 2008.09 release of Design Compiler®, MCMM is now also available in logic synthesis. In this paper we will apply MCMM constraining in logic synthesis with Design Compiler®. Objective of this work is to analyze and evaluate benefits and drawbacks of multi-corner multi-mode synthesis in Design Compiler®. To do this we synthesize a 170k standard cell testcase in umbrella mode and MCMM style. In MCMM style 2 – 5 scenarios are applied. The resulting netlist is placed and routed in IC Compiler®, again either in umbrella or MCMM style. Finally, the resulting timing is analyzed in PrimeTime® and the obtained results with respect to timing, area, and power are compared. Our experiments show that using the MCMM feature of Design Compiler® does not improve final quality of results. Timing and area results just depend on the modes and corners active in IC Compiler®, but do not depend on the applied scenarios in Design Compiler®. Moreover, using additional scenarios in Design Compiler® increases cpu-time and memory requirements. Benefit of using MCMM in Design Compiler® is definitely the consistency of the applied constraints throughout the implementation flow. Additionally, using MCMM in Design Compiler® enables the user to identify timing critical paths and scenarios early in the implementation phase. In conclusion, we recommend some criteria to the user to ease decision making for or against usage of MCMM in Design Compiler® dependent on project characteristics.
|A2 User Session - Implementation: Place & Route I|
|Inserting and Integrating Level Shifters during Physical Implementation (ICC)|
Kousalya Nagakarthick, Ralph Sommer [LSI Logic GmbH]
This paper describes how to insert Level Shifters late in the design flow at ICC level using insert_mv_cells. The setup challenges, both design specific and tool specific in ICC and the required physical design know-how on the frontend UPF flow for achieving a smooth Low Power implementation of Low Power cells in ICC and power mesh implementation in ICC will be discussed.
|Mixed-Vth Leakage Optimization in the Final Design Stage - Experience with new Final-Stage Leakage Recovery Flow|
Robert Häußler, Mihael Murković [Lantiq Deutschland GmbH], Anders Lind [Synopsys GmbH]
Low leakage is a key target in Lantiq’s low power design strategy. One standard measure to reach this is mixed Vth optimization. For this task Lantiq used the new IC Compiler “Final-Stage Leakage Recovery” flow on a productive chip, where an impressive high share of high-Vth cells could be achieved. The feature runs in the final design-stage on a sign-off clean database. This can speed up the design cycle time by using a regular- or low-Vth library only, to meet timing first and bring in the high-Vth cells in the final stage.
|Using Synopsys IC Compiler for DFM optimization at 28nm|
Rainer Mann, Ulrich Hensel, Vito Dai, Shobhit Malik [GLOBALFOUNDRIES], Jens Peters [Synopsys]
Physical design rules are increasing in number and complexity for advanced technology nodes such as the GLOBALFOUNDRIES’ 28SLP process. This alone implies severe challenges to achieve design rule closure while meeting design constraints such as density, timing, power and signal integrity goals. DFM specifies another optimization target that place and route tools need to approximate or satisfy by utilizing layout opportunities without sacrificing on either the mandatory physical design rules or the design constraints. DFM Rule modeling often differs from the modeling of classic ground design rules and, therefore, adds requirements that modern routers need to satisfy.
This paper details how IC Compiler Zroute can be utilized to efficiently implement DFM rules. Further it demonstrates how IC Validator can detect lithographic hot-spots using GLOBALFOUNDRIES’ DRC+ pattern matching library and how IC Compiler can repair these through integrated ECO-loops. The shown results and script examples should enable the readers to comprehend and adopt the described methodology into their design flow.
|A3 Tutorial & User Paper - Verification & IP: Digital Verification|
|Method for Reusable Low Power Mode Entry/Exit Verification Applied on Freescale S12 uC|
Joachim Geishauser, Alexander Schilling, Andreas Pachl [Freescale Halbleiter Deutschland GmbH]
Increasing design complexity and the demand to keep power consumption low gave rise to various design techniques in order to achieve this goal. Verification of these designs becomes an even more complicated task. Verification languages provide features to ease the job of verification, however without a methodology around them the verification task will become a nightmare. The methodology presented in this paper describes the infrastructure such as the abstract low power verification classes and a verification process for entering low power states as well as the wake up from them. In the paper the low power techniques are the traditional ones but an outlook will be given on how this can be scaled to the latest techniques. On the SoC level the paper will show how this approach addresses the verification problem in a reusable way.
|A4 User Paper & Tutorial - AMS/Full Custom: AMS Verification I|
|A Simple but Effective and High Accurate Parasitics Estimator for Prelayout Parasitic Estimation|
Hendrik Mau [GLOBALFOUNDRIES]
With more and more shrinking design dimensions the impact of interconnect parasitics on design performance is increasing. This results in the necessity to estimate the interconnect parasitics as accurate as possible during early design stages. To avoid costly design adaptation after post layout verification it is beneficial to estimate the interconnect parasitics at the stage of schematic entry or verification.
Typically more or less complex wire load models or equations are used to model the parasitics. They all require abstraction and curve fitting resulting in a loss of accuracy. A simple method is proposed which uses the RC techfile available with the PDK and StarRC directly to determine the wire resistance and capacitance by means of a simple and fast extraction flow. Hereby a simple DEF is written for the desired wire configuration which is than handed over for parasitic extraction to StarRC. Within seconds StarRC can extract this structure and the estimated resistance and capacitance is available.
|Circuit Check: Discover Circuit Design Errors in Low Power SoCs|
Luong Nguyen [Synopsys France]
System-on-chip in low power leads to adopt different methodolgies to increase the verification coverage. A high consideration of the power consumption becomes a key factor to enhance the overall quality of the circuit. Hence it is crucial to detect as soon as possible any potential leakage current. The tutorial is intent to present some typical design errors found in multi-power domain applications and the benefit on using HsimPlus Circuit-Check to detect potential errors earlier during the design cycle.
Target audience: Custom/analog/mixed-signal designers.
|A5 User Session & Tutorial - System: High Level Synthesis & Verification|
|Employing Synphony Model Compiler with Application Components for FPGA Processing Elements in Software Defined Radios|
Peter Troll [Rohde & Schwarz GmbH & Co. KG]
Software Defined Radios (SDR) are distributed processing systems including General Purpose Processors (GPP), Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGA) as processing elements.
An SDR is characterized by clearly differentiating between two portions of software. There is the application software and also software that provides the infrastructure for an application to execute and access system hardware resources. Originally promoted for the military domain and increasingly considered for commercial use, the internationally endorsed open Software Communications Architecture (SCA) standard has been developed, supporting the specific aspects of SDR platforms and applications.
This paper presents the multifaceted considerations in adopting a High-Level Synthesis tool for developing application components targeted at FPGA. The conclusion reached is to establish Synopsys’ Synphony Model Compiler as first choice within Rohde & Schwarz.
|Formal Verification and Validation of High-Level Optimizations of Arithmetic Datapath Blocks|
Theo Drane [Imagination Technologies Ltd.], Himanshu Jain [Synopsys, Inc.]
Datapath verification and validation offer considerable challenges throughout the design process, whether this is proving equivalence along the chain of models: system-level, RTL and gate-level or validating the design itself. Using the latest word-level equivalence checkers, such as Synopsys’ Hector, it is possible to bridge the gaps between these models and perform validation. For the designs considered, equivalence checking between system-level and RTL models using simulation would take longer than the entire design cycle. Using Hector, we can formally check the equivalence between these designs in reasonable time. For example, a double precision floating point multiplier would take years to simulate exhaustively but can be proven correct in 82 seconds.
|Recursive Hierarchical Compilation using Synphony C Compiler|
Frédéric Génin [Synopsys France]
One goal of high-level synthesis is to synthesize C/C++ code into efficient hardware implementations while keeping the input coding style as simple as possible. This session looks at examples in image and video processing that illustrate more advanced high-level synthesis optimizations that enable larger and more complex C/C++ algorithms to be synthesized efficiently in ASICs and FPGAs. These HLS features can achieve much higher productivity for both design and verification of video and imaging hardware.
Target audience: RTL designers, verification engineers, system architects, algorithm designers.
|A6 Tutorials & Demo - Automotive: Introduction & Overview|
|Automotive System Electrification through Virtual Design & Verification: Synopsys Solutions & Directions|
David W. Smith [Synopsys, Inc.]
The biggest challenge for the automotive industry this decade is the electrification of the vehicle. This requires the re-architecture and design of most of the automotive systems. The challenges start with the electrical system including wiring, power generation and distribution, and all of the loads. It progresses through the electrification of the power train. And includes the continued expansion of software controlled embedded systems throughout the vehicle. The combination of power and processors has resulted in the most complex consumer system available in the world. At the same time improving the reliability of these complex systems is a major challenge. Synopsys provides a range of solutions that address challenges from the silicon level through the automotive systems.
Target audience: automotive OEMs, Tier 1, and Tier 2 suppliers.
|Assisting Virtual Prototyping with Hardware Based Methods|
Robert Eichner [Synopsys GmbH]
Combining virtual prototyping with Hardware based verification methods is not only an enabler for system verification as it closes the model availability gap. It also adds new capabilities by using the VP as a testbench or, vice versa, allow real physical IO being used in a VP. This tutorial shows the possibilities, capabilities and limits of such a hybrid solution as well as a demonstration of it.
|A6 Tutorials & Demo - Automotive: Introduction & Overview |
|Incremental Design Flows for Highly Complex FPGA Designs|
Philipp Jacobsohn [Synopsys GmbH]
FPGAs are growing in complexity at an alarming rate and are now the primary drivers for new process technologies. Today’s FPGAs contain the equivalent logic capacity of a 5 million gate ASIC design plus 30Mb RAM and various IP such as Gigabit I/O, DSP blocks and microprocessors. With this complexity new design methodologies are required that enable the design engineer to reach timing goals quickly and accurately. The Synplify Premier synthesis tool has been improved in order to address these new requirements. Advanced technologies were integrated into the tool that provide Results Preservation, Incremental Flows, Easy IP Integration, Runtime Acceleration, Multiprocessing, and Hierarchical Flows.
|Thursday, May 19, 2011|
1:15 PM - 2:45 PM
|B1 User Session - Signoff: STA and Constraint Analysis|
|Galaxy Constraints Analyzer Evaluation|
Sönke Grimpen [Infineon Technologies AG]
Having correct timing constraints during sign-off is critical. Using more sophisticated models during implementation enhancing convergence and correlation with final sign-off making it necessary to have good timing constraints from the beginning. Galaxy Constraints Analyzer provides extensive checking capabilities combined with the user interface and constraints understanding from PrimeTime. Having worked with GCA in alpha and beta phase, evaluated it and integrated it into our design flow, this session discusses our experiences and results.
Sönke Grimpen [Infineon Technologies AG]
Static Timing Analysis is fast and exhaustive. Why? This workshop is describing the underlying principles and the differences between simulation and STA, where it’s wrong, but useful. It describes the two steps in STA, delay calculation and the timer. Terms like “timing graph”, “timing arc”, “timing paths” and “slack” are explained and how they can be found in a simple timing report.
|Path-based Analysis : A Realistic Solution to Unrealistic Timing Paths in Complex ASICs|
Satinder Paul Singh, Farid Labib [LSI Corp. Germany]
In this paper we like to show the benefits of using Primetime’s Path Based Analysis (PBA) for sign-off static timing analysis of a very large, hierarchical design. The motivation to use the PBA approach is to save project schedule by closing none closable timing paths. Different problem scenarios and their resolution with PBA are shown. A semi-automated way to incorporate PBA into our flow will be presented. An appendix allows the reader to dive into the details behind PBA.
|B2 Tutorials - Implementation: Place and Route II|
|Template-Based Power Planning in IC Compiler|
Jens Peters [Synopsys GmbH]
This tutorial will introduce the next-generation power network planning technology within IC Compiler for both multi-voltage and non-MV designs. With template-based Power Network Synthesis (PNS), users will have a more control in creating state-of-art power/ground (PG) structures. The tutorial will also describe the different categories of user inputs for PG creation - design dependent (strategy) and design independent (template-based). The design dependent piece is to define power network topology while the reusable template-based input is to fine-tune power mesh configuration.
Target audience: Physical designers and managers.
|Eliminating Late-Stage Manual Fixes with In-Design Physical Verification|
David DeMarcos [Synopsys Italy]
As device geometries continue to shrink, the number and complexity of design rule checks (DRC) to achieve manufacturing compliance are rapidly growing, leading to an increasing number of post-route violations. Traditionally, such violations have required manual layout fixes, which are time-consuming and can impact design convergence. In this session, we will demonstrate how in-design physical verification with IC Validator enables Automatic DRC Repair (ADR), a novel capability that makes it possible for designers to automatically detect, repair and revalidate signoff DRC violations – all within IC Compiler.
Target audience: Design and CAD engineers and managers responsible for physical implementations.
|B3 Tutorial & User Session - Verification & IP: IP integration|
|VCS ProductivityTools and Technologies that Help Reduce the Ever-Growing Verification Cycle|
Werner Kerscher [Synopsys GmbH]
In this tutorial you will learn how to apply the latest VCS technologies to improve your verification turnaround time and meet your project deadlines. We will teach you how to speed up your compile and runtimes while decreasing your debug and coverage cycles.
Target audience: Verification engineers, CAD engineers, and project managers interested in learning how to reduce verification time.
|Chips and IPEAS - It’s not Mushy|
Jonathan Young [Synopsys Ltd.], Presenter: Steve Lloyd [Synopsys Ltd.]
Chasing Moore’s law has required the development and use of high value interface and IP sub-systems to address the integration complexity required by the next generation of SoC’s. Yet even using the highest quality IP available designers should not underestimate the challenges, both logical and physical, of integrating, verifying and implementing separate IP blocks to form com-plete systems. Drawing on many years of SoC design experience and more than 50 tape-outs from Synopsys Professional Services this paper describes these challenges, their solutions and what to look out for when selecting and designing with IP.
|Evaluation of an on Chip Bus Fabric Solution Based on Synopsys IPs|
Bogdan Sbarcea [Siemens Romania], Majid Gameshlu [Siemens Austria], Andreas Vielhaber [Synopsys GmbH]
The concept of an on-chip interconnect has become a key requirement for integration of reusable IP components in today’s SoC Designs. With high bandwidth requirements and the need to bring high performance IP blocks into the design to keep up with Moore’s Law a proven, and flexible interconnect is required. Some of the most important advantages of such an interconnect structure need to be: high bandwidth, simplified routing, area reduction as well as scalability and customizable arbitration.
|B4 Tutorial & Demo Session - AMS/Full Custom: AMS Verification II|
|Introducing CustomExplorer Ultra|
Dwayne Holst [Synopsys, Inc.]
Introducing CustomExplorer Ultra - a comprehensive automated mixed-signal regression and analysis environment for CustomSim and CustomSim/VCS co-simulation. There are many challenges in mixed-signal verification: thousands of simulations to setup and manage, complex test bench and corner setups, and a massive amount of data to analyze. In addition, multiple data formats, languages, and simulators need to be supported. This tutorial will show how CustomExplorer Ultra addresses these challenges and can increase mixed-signal verification productivity while also simplifying the process.
Target audience: Custom/analog/mixed-signal designers.
|AMS-Testbench: An Innovative Methodology for Verifying Mixed-Signal Components|
Fabian Delguste [Synopsys France]
As the size and complexity of the analogue and mixed signal content on modern SoC designs increases, there is a growing need for a unified truly mixed signal verification flow. Verification methodologies such as VMM and UVM have become well established for digital verification. This tutorial will describe how these techniques can be expanded to include the verification of the analogue content on an SOC using VCS-AMS testbench.
Target audience: Custom/analog/mixed-signal designers.
|B5 User Paper & Tutorial - System: SoC Architecture Design|
|Developing High-performance Wireless Systems by Combining Virtual Prototype Models|
Yvonne Gsottberger, Josef Eckmüller, Helmut Reinig [Intel Mobile Communications Germany]
Well-known in system development processes is the usage of prototype C models for faster system verification and the development of system software on those hardware prototype models. Therefore already exhaustive C model libraries exist in system architecture departments as well as the appropriate simulation environments, like Synopsys’ VAST. Another approach to speed up system development, namely in the phase of architectural decisions, is the usage of abstract models which are enhanced with performance critical data to ease architecture exploration based on realistic processor frequencies and data traffic in the system. Such SystemC models are simulated in our department in a special environment named SystemQ to rapidly gather statements on an expected system performance. Preferably, those performance simulation models should be re-used as prototype models for system verification and software development, also. In this paper we want to present how existing C- and SystemC models are combined together in the VAST environment. The advantages of such a solution are: 1. an existing fast simulation environment can be used for regression and performance estimations, 2. existing IP models can be used throughout the complete regression, and 3. further regressions can be done on a more accurate basis regarding data traffic, bottlenecks, and possible dead locks, as the SystemQ performance models are especially modelled for estimations on maximum reachable system speed and data throughput. We will present the method how we bridged SystemC and C models taking XBARs as design example, introduce the generation setup for the necessary adapters, and explain how the SystemQ parameter files are integrated into the VAST simulation environment.
|Performance Analysis for AMBA-Based SoC Design|
Gunnar Braun [Synopsys GmbH]
The massive growth in system integration places on-chip communication and interconnect at the center of system performance. Using spreadsheets to statically estimate bandwidth is not viable, as dynamic workloads make it impossible to predict performance across all configurations of the interconnect and memory subsystem. More and more, architects are using system-level design methods to predict system performance earlier in the design cycle, enabling new SoC designs to meet their performance objectives while avoiding the risk and cost of over-design. This tutorial walks through a case study demonstration of system-level performance analysis and optimization featuring Synopsys Platform Architect, the Synopsys SBL-301 SystemC Bus Library for the ARM CoreLink NIC-301 Network Interconnect, and ARM CoreLink ADR-301 AMBA Designer.
Target Audience: System Designers, Product Architects, SoC Architects, Project Managers
|B6 Combo Session - Automotive: Automotive System Design & Analysis|
|Electrical Function & System Development of Commercial Vehicles at Volvo using Saber|
Samuel Alinder [Volvo Sweden]
Electrical Function & System Development of Commercial Vehicles at Volvo using Saber Development and validation of 24V heavy truck electrical platform.
Creating and reusing functions from draft block schematic to full electrical schematic to Wiring Harnesses in the same tool.
Validate power management in a 24V system with multiple power modes.
|SABER Simulation of Electric Actuators|
Dr. Szabo, Dr. Moule [TRW Automotive Systems]
The paper "SABER Simulation of Electric Actuators" will show how TRW uses SABER for the modelling and simulation of automotive electric actuators. Modelling and simulation is part of the concept design and development process. The models developed are verified experimentally and are used to analyse both steady-state and transient operation and performance, as well as to investigate failure modes.
|Setting up an Enterprise-wide Automotive Model Library - Potentials, Requirements and Challenges|
Armin Schön [Continental Automotive Systems GmbH]
A common simulation model library for sure brings a large benefit for the company's engineers. Administrative tasks and data management are taken care of from a central department and more models are available for the users. Nevertheless the demands of different projects and organizational units are quite different. How can the different requirements be met while keeping the effort acceptable? Let us think about it.
|Thursday, May 19, 2011|
3:00 PM - 4:30 PM
|C1 Tutorial & User Session - Implementation: Low Power|
|New Multi-Voltage Power Optimization Techniques to Address Power Reduction During Design Implementation|
Michael Confal [Synopsys GmbH]
This tutorial describes the usage of specific Multi-Voltage (MV) features, introduced in the E-2010.12 release of Design Compiler and IC Compiler. The following features will be highlighted:
- New features in Galaxy Low Power
- High level abstract way to specify power intent in place of using specific physical power supplies
- Fine methods to control level shifter and isolation cell insertion
- Flexible Power Management Cell Insertion
Target audience: All low power implementation designers
|Hierarchical UPF Implementation and Verification|
Mario Orgis [Intel Mobile Communications Germany], Knut Dalkowski [Synopsys GmbH]
UPF-based implementation is part of Intel Mobile Communications standard implementation flow today. This paper discusses the implementation of a hierarchical cellular baseband design with UPF. In a bottom-up approach, power intent is developed for each sub-block, employing different power strategies such as shutdown, low-VDD standby and nested always-on domains. ILM hierarchical models with UPF information are generated and integrated into the chip top-level. The UPF setup to handle retention memories, isolation cells located in the parent domain outside the ILMs as well as the handling of always-on exception connections will be discussed.
|C2 User Paper & Tutorial/Demo Session - Test: Compression and Volume Diagnostics|
|Improving DFTMAX Compression Results in Latch Based Designs|
Richard Illmann [Dialog Semiconductor]
In a scan tested design non-scanned elements can create X-states. In conventional scan architecture these can degrade test coverage and increase pattern count. However, if DFTMax compression is used the impact is much greater because the output compressor uses XOR trees. Even with X-state masking the results can be severely degraded and the achieved level of compression decreased. This paper describes design techniques and features within Tetramax for minimising the X-states. The results of the techniques are shown on a mixed signal audio processing chip.
|Volume Diagnostics: The Key to Faster Yield Ramp at Nanometer Node Technologies|
Nikolaus Mittermaier, Christophe Suzor [Synopsys GmbH]
The sub-100nm node technologies are known to be progressively susceptible to systematic yield loss caused by design-process interactions. Such interactions occur at very specific combinations of design geometries and process conditions, mostly in logic blocks of the design, and thus are very difficult to capture quickly. Volume Diagnostics is the best possible methodology to address such issues during the yield ramp for the new products, as well as for investigating customer returned field failures. Learn how the Synopsys solution, with TetraMAX Diagnostics and Yield Explorer, offers the most comprehensive Volume Diagnostics capability with an automated PFA (Physical Failure Analysis) list extraction. The Yield Explorer PFA application drives identification of the dominant systematic failure mechanisms on a new or field returned devices at 10x faster time-to-results.
Target Audience: Product Engineers, DFT Engineers, DFM-CAD Engineers, Failure Analysis Engineers, Foundry Managers
|C3 Tutorial - Verification & IP: Processor Cores|
|Configuring DesignWare ARC Processors to your Embedded or Host SoC Application|
Martyn Bronziet [Synopsys Ltd.]
Today’s SoCs are significantly more complex, resulting in a number of challenges for designers including increasing development costs, the need for greater programmability, higher-performance demands, reduced power, and market cycles that are getting shorter decreasing development schedules. To address these challenges DesignWare ARC processors offer a broad range of capabilities from very high performance to very small size, and are highly configurable and extensible. They are an ideal solution for multicore designs, and can be quickly implemented and customized for each instance on an SoC for embedded and host processing. This session will discuss how DesignWare ARC processors help designers meet their performance targets, increase battery life, and control costs, while reducing integration risk and speeding time-to-market. In addition, the hardware and software development tools for the processor, including the latest ARC Android port will be discussed.
Target audience: This is targeted at designers that are developing SoCs for embedded applications that require 1 or more 32-bit processors.
|C4 User Paper & Tutorial - AMS/Full Custom: Analog Implementation|
|Deployment of Custom Designer for the 40nm Design Flow at Lantiq|
Michael Wagner, Johannes Rauh [Lantiq Deutschland GmbH], Oliver Bär [Synopsys GmbH]
The ever increasing complexity of SoC designs caused by the drastically higher number of diverse & complex on chip building blocks (IP, analog, mixed-signal) requires a much tighter integration between full-custom and semi-custom methodologies. We are convinced, that such a tight integration can only be developed when the main semi-custom tool – IC Compiler in our case – and the full-custom environment are from the same company. That’s why we decided to integrate Custom Designer as the single solution in our new 40nm design flow and are currently deploying it as part of 3 different projects.
This paper will focus on the steps performed to integrate Custom Designer, HSpice, Custom Explorer and the interoperable Process Design Kits (iPDK) into our CAD flow by efficiently customizing the tools to our needs.
|Synopsys Custom Design Solution|
Oliver Bär [Synopsys GmbH]
Custom IC design is a critical component in many design projects as technology and market forces drive towards increasing inter-dependence between digital and analog portions. This tutorial will introduce attendees to Synopsys’ comprehensive custom design solution with an integrated demonstration of Custom Designer, HSPICE, CustomSim, WaveView, IC Validator and StarRC. The tutorial will give special emphasis to significant new capabilities in the simulation environment as well as new layout automation.
Target audience: Custom/analog/mixed-signal designers.
|C5 User Paper & Tutorial - FPGA: HW Assisted Verification|
|FPGA-based Validation of TV Signal Demodulation Algorithms Using the Xilinx Virtex-6 based HAPS-62 Platform|
Rolf Nöthlings [Sony Deutschland GmbH]
There are numerous different standards for TV signals worldwide. During the development of digital signal processing (DSP) applications for TV signals it is necessary to validate correctness and efficiency of algorithms in many modes and environments.
This paper presents the development of an FPGA-based platform for validation of a design for de-modulation of digital and analog TV signals. FPGA-based prototyping platforms assist the development and validation of DSP algorithmic content because they can be used to test the correctness of algorithms in a real-world environment, in real-time.
The FPGA platform provides not only the same functionality but also runs at the same system clock as the intended final ASIC component.
|Advanced Capabilities and Design Interaction with FPGA-Based Prototyping|
Mick Posner [Synopsys, Inc.]
In order to boost the utility of an FPGA-based prototyping platform, certain critical components are required, including a high-performance, low latency communication channel and direct access to all pins, signals, nodes and registers within the FPGA. Discover how the advanced capabilities of Synopsys HAPS® High-performance ASIC prototyping system ™ and the new Universal Multi-Resource Bus interface (UMRBus) improves the overall design, verification and software development of an ASIC or SoC.
|C6 Combo Session - Automotive: Virtual Prototyping of HW/SW Systems|
|Virtual Platform for a Chassis and Safety Application|
M. Thanner [Freescale]
This presentation will give an overview about the development and deployment on a virtual platform used in electronic stability control application for pre-silicon software development, design exploration and performance analysis. The presentation will give an overview on the used simulation technologies, example model implementations and coupling technologies. The deployed software use cases will be shown and how it accelerated the development process due to pre-silicon availability.
|Demo: A Virtual e200 Multicore Microcontroller|
Gunnar Braun [Synopsys GmbH]
The demo shows a Virtual Prototype of a subset of Freescale's MPC5668 MCU. It shows how a Virtual Prototype enables e.g. AUTOSAR-aware debugging, advanced HW and SW analysis, and fault injection.
|Leakage Power Optimization Flow for Low Power Designs|
Ramy Gamal [Dubai Circuit Design]
|Synthesizable Verification IP to Stress Test System-on-Chip Emulation and Prototyping Platforms|
Xu Bing Tao, Jayaratnam Siva Shankar, Subramanian Shiva Shankar [Lantiq]