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| MA1 - Coverage |
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CovVise: How We Stopped Throwing Away Interesting Coverage Data
Wilson Snyder [Veripool.org], Robert Woods-Corwin [NVIDIA] |
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Jazz Up Your Coverage Reports with VMM Planner
John Stiles [Silicon Logic Engineering] |
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| MA2 - XA |
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XA Verification in Implantable Medical Design
Garrett Marshall, Jalpa Shah, Scott Stanslaski [Medtronic], Joseph Perttu [Synopsys] |
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LSI Transistor-Level Verification Using XA
Amy Rittenhouse, Jianjun Liu, Richard Stephani, Andrew Cable [LSI Corp.] |
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| MA3 - Easier Design Closure Using DC and DCT |
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Stop Being Passive - Be Active with DCT
Christopher Krueger [STMicroelectronics], Alex Fatehali [Synopsys, Inc.] |
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RTL Structural Analysis Using Design Compiler
Pete Nixon, Paul Rotker, Matt Cohen, Keith Morse, Bandish Shah [Sun Microsystems] |
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| MA4 - ICC Usage |
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Predictable and Repeatable Feedthrough Floorplanning Using ICC
Franklin Bodine, Chris McGlone, Duane Galbi [Intel Corp.] |
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The Benefits of MCMM with Multi-Corner Timing Closure
Tim Houlihan [Cypress Semiconductor] |
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| MA5 |
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Tips and Tricks for FPGA Synthesis, Debug, and Faster Turnaround Time
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| MA6 |
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Power-Aware DFT/ATPG and Technical Updates
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| MB1 -SystemVerilog & VMM |
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E To SystemVerilog Conversion
Premkishore Shivakumar [Intel Corp.], Alex Wakefield, Jason Chen [Synopsys, Inc.] |
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SystemVerilog's Virtual World - An Introduction to Virtual Classes, Virtual Methods and Virtual Interface Instances
Clifford Cummings [Sunburst Design, Inc.], Heath Chambers [HMC Design Verification, Inc.] |
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Building a Best Practice VMM Interface VIP Template
Ning Guo, Jeff Wilcox, Rich Musacchio [Paradigm Works] |
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| MB2 - HSPICE and HSIM |
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How to Get Maxwell and Kirchhoff to Shake Hands Using HSIM/WaveView for EMI Analysis
Cornelia Golovanov [LSI Corp.], Cheung Lam [Synopsys] |
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HSPICE Aided S-Parameter Embedding and De-Embedding for High Speed Interface Compliance Testing
Johann Nittmann, Frank Corcoran [Cavium Networks] |
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Multi-Gigabit Serial Link Analysis Using HSPICE and AMI Models
Douglas Burns, Barry Katz, Walter Katz, Mike Steinberger, Todd Westerhoff [SiSoft] |
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| MB3 |
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Design Compiler Graphical - Addressing Routing Congestion During RTL Synthesis
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Verifying Power Intent with MVRC & Formality
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Advanced Synthesis Methodologies with the Lynx Design System
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| MB4 |
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ECO Flows Using ICC
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In-Design Physical Verification for Faster Time-to-Tapeout and Improved DFM
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| MB4 - ICC and IC Validator |
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Design Rule Check Classification System with IC Validator
Pavel Rott [Intel Corp.] |
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| MB5 |
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CHIPit Use Models for Hardware Verification and Validation
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| MB6 - Test |
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Small-Delay Defect Testing of a High-Volume Server
Francisco Duran-Urrea [Advanced Micro Devices], Don Skinner [Synopsys, Inc.] |
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Testing Latch Dominated Designs from a Mixed-Signal and Low-Power Domain
Richard Illman, Hans Martin von Staudt [Dialog Semiconductor] |
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Breaking the Hierarchy Rules: An Advanced Hierarchical DFT Strategy for a 5 Million Flop Design
Charles Njinda [Cisco Systems] |
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| MC1 Simulation and Testbenches |
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Innovative Testbench Approach for Multi-ASIC Simulation
Martin Blouin [Cisco Systems] |
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Accelerating Simulation Performance using VCS in a CPU/GPU Integrated Verification Environment
Sonu Arora, Madhuri Nallapaneni, Alex Miretsky, Peter Chi Wing Ng [Advanced Micro Devices] |
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| MC2 |
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Solving Signal Analysis Challenges with WaveView
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| MC3 - Agile Programming and MVSIM |
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Low-Power Verification of Multi-Rail Cells in RTL
Ramanan Balakrishnan, Borhan Roohipour, Balakrishnamohan Kanukollu [Advanced Micro Devices], Vikram Malik, Tushar Parikh [Synopsys, Inc.] |
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A Giant, Baby Step Forward: Agile Techniques for Hardware Design
Neil Johnson, Bryan Morris [XtremeEDA Corp.] |
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| MC4 |
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Handling Very Large Designs in ICC Using a Reduced Netlist Flow
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| MC4 - Zroute and IC Compiler |
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To Z or not to Z
Jeff Shi [LSI Corp.] |
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| MC5 |
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Synplicity - New Technology for ESL Design and FPGA Synthesis
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| TA1 |
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Interactive Coverage Analysis and Exclusion with DVE and URG
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| TA2 |
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Synopsys' Custom Design Solution
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| TA3 |
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What's New in PrimeTime 2009.06
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What's New in Design Compiler 2009.06
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| TA4 |
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Improving RTL-to-GDSII Design Efficiency with Lynx Design System
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| TB1 |
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VCS 2009.06 Update
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VMM 1.2 Introduction
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VCS Performance and Memory Profiling
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| TB3 |
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What's New in IC Compiler 2009.06
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| TB4 |
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Power Analysis
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Faster Timing Closure in a Multi-Scenario World
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Advanced On-Chip Variation
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