|Tuesday, June 11, 2013|
9:30 AM - 9:30 AM
|Accelerating Innovation in the Era of Electronics That Touch Everyone, Everything, Everywhere|
Chi-Foon Chan, President and co-CEO - Synopsys
Technical innovation is increasingly touching everyone, everything, everywhere with today’s consumers wanting it all: 24/7 connectivity, unlimited bandwidth, data, entertainment, security, portability and more. As this exponential trend continues, engineers designing the chips and systems inside of these electronics must adopt new technologies and strategies in order to deliver ever faster, lighter, smarter and cheaper products in record time. Dr. Chan’s presentation will provide insights on how to accelerate innovation in the era of electronics touching everyone, everything, everywhere.
|Tuesday, June 11, 2013|
10:45 AM - 12:15 PM
|A1 - Functional ECO Automation & UPF Implementation|
|Leveraging Formality ECO Flow to Speed up Last-Minute Change Verification|
Laurent Besson - ST-Ericsson
Equivalence checking is a fundamental step in digital design flow quality. It ensures gate netlists, after synthesis or physical implementation, still have the same functionality as the original RTL design (as proved by functional verification). This flow is today perfectly handled by Formality and is part of any decent reference digital design flow.
What becomes more complex is how to handle last minute changes (also known as ECO) where the schedule is too tight to re-execute the full flow and only manual or semi-automated changes are performed on back-end netlist. The need to prove the final netlist after ECO versus the proven RTL is still mandatory. Formality is today proposing more automation to handle the ECO flow while keeping affordable runtime of execution.
This paper will describe the problems seen in the past, will cover this new methodology and provide details on real design data and metrics. It will also describe the weakness of this flow and propose enhancements for the future.
|Taking Advantage of UPF2.0 for Advanced Low-Power Techniques|
Frederic Saint-Preux - STMicroelectronics
UPF1.0 was initially introduced by the Accellera Committee to separate the power intent from the design functionality, moving from an instrumented RTL to un-instrumented RTL. This language introduced higher productivity using a single format through the entire flow with consistent semantics for implementation and verification.
However the increasing complexity of low-power technology requested in the most advanced low-power designs opened the path to adopt new functionalities introduced in UPF2.0.
This new and extended format brings a higher level of abstraction but raises new challenges.
This paper will detail the approach used today at ST in order to transition smoothly to UPF2.0 as an incremental description of the power intent. In this paper, we will share real examples of limitations faced with UPF1.0 and how UPF2.0 is solving them. We will also see some limitations of UPF2.0 and how they could be answered in the future UPF2.1 standard.
|Converting an Outdated Library for UPF Compliancy Prior to a Low-Power Physical Design that uses Retention Flip-Flops|
Etienne Wouters, Ilse Vos - IMEC
Most nanometer ICs require nowadays low-power design techniques based on UPF descriptions that Synopsys tools can handle efficiently.
But what do you do if you want to apply those design techniques to slightly older technology nodes, of which library views were not designed for?
This paper describes a detailed flow for converting an outdated Milky Way library, which traditionally doesn’t contain accurate PG information, into a timing equivalent library that fully supports physical design based on UPF requirements. Afterwards, the reader is guided through several points of attention and helped for troubleshooting along the consecutive steps of a low-power flow: DC, DFT Compiler, ICC, Formality and MVRC, what can be considered as a valid sequence for QA on the converted libraries.
Although most cells used in low-power designs are addressed (coarse grain switches, level shifters, isolation cells) a closer focus is paid on Retention Registers, since this technique has still to conquer a significant part in the users community.
|A2 - Accelerating SoC Verification|
|"Coverage-Driven" ASIC Verification Environments Coupled to an SQL Database|
Stephane Thoison - Bull
Nowadays it is common to encounter some "coverage-driven" verification environments associated with pseudo-random tests.
BULL doesn't derogate to that trend and has built an internal SystemC verification framework based on functionnal coverage that eases deployment of a common verification strategy shared over several projects.
In parallel, BULL decided to use an external SQL database as a central storage for all verification metrics.
We take benefit of that database, its responsiveness and availability, to dynamically adapt regression campaigns and simulation runs, to natively support functionnal verification testplan that can be online crossed with functionnal coverages embedded into logical simulations.
Finally, metrics extracted from SQL database and collected from various simulation tools, highly participate to our ASIC verification closure.
|Accelerating SoC Verification with Synopsys Discovery VIP and the ARM CCI-400 Cache-Coherent Interconnect|
Xavier Mathes - Synopsys
Your next project contains multiple processors connected by the ARM® CCI-400 Cache Coherent Interconnect, and you need to verify it, pronto! This tutorial shows how to get up to speed quickly with Synopsys Discovery VIP, focusing on the AMBA® 4 AXI4™ and ACE™ bus protocols. You will see how the Reference Verification Platform (RVP) helps you connect the VIP models to the interconnect, configure the system, and debug with Discovery Visualization Environment (DVE) and Protocol Analyzer. Learn how to inject errors with UVM callbacks, and reach your coverage goals with Smart Sequences. Spend less time learning the tools and methodology, and instead focus on verifying your SoC.
Verification and Design Engineers and Managers.
|A3 - Advanced Topics for Design Closure|
|Advanced CTS Techniques for High-Performance Mobile Designs|
Frank Vaneerdewegh - ST-Ericsson
The paper describes how advanced clock tree synthesis techniques can be implemented within Synopsys IC-Compiler to improve the QoR (power and skew) of a high-performance mobile design. It addresses how Multisource Htree CTS, multisource Mesh CTS and conventional CTS are implemented and how important QoR parameters are related depending on the configuration used. The paper also addresses how power and timing can be measured in multisource Mesh CTS. Due to the nature of Mesh, which is shorting the drivers output, standard flows cannot be used and analog simulation is needed for power and timing annotation.
|28nm FDSOI Leakage Optimisation with Synopsys Flow|
Pascal Teissier - STMicroelectronics, Nathalie Zaghlan - Synopsys
Emerging design challenges mandate a new leakage optimisation approach. Market requirements increase design complexity in terms of frequency/size and power. In this context, product consumption must be minimized (impacts battery size and power life, product efficiency, package choice, ...). Thus, leakage becomes a key parameter and needs to be monitored and/optimized throughout the implementation flow.
This article will describe leakage optimisation and techniques used for high performance core implementation in 28nm FDSOI technology. It will cover leakage optimisation key features available in ICC (place_opt/route_opt) and give more details on Galaxy leakage recovery capabilities (focal opt and PrimeTime ECO). This last feature allows to minimize leakage by taking advantage of the signoff environment (accuracy and multi-scenario), leading to a significant leakage gain.
|Light Advanced on Chip Variation Approach|
Pierpaolo De Laurentiis - STMicroelectronics
Stage-based OCV derate tables are a systematic correction for on-chip process variation, to give in timing and optimization tools a fast way for more accurate results and helping to close timing at smaller process nodes. Existing AOCV technology is exploited to enhance existing SO flow.
The 'LightAOCV approach' is introduced to characterize silicon and use it within a PrimeTime AOCV environment. In this approach, all the contributors for the derating are computed only on a stage-depth base, using a ST-proprietary SPICE-based tool to extract derating factors for different sets of clock cells. A custom Kit for AOCV is also introduced, to record the results from the silicon characterization and propagate into several designs the correct derating factors, according to the possible project cases.
|A4 - Design for Test and ATPG|
|Reducing the Tester Resources using Shared IO for a Quad-Core OpenGL ES GPU|
Fabrice Rieu - STMicroelectronics
In few years, multi-core usage becomes a solution to performance and scalability. It adapts dynamically the power consumption, allowing extended autonomy for mobiles devices and a choice of cost-effective packages without heat sink.
Hard trade-off between dedicated scan access pads, embedded product features, and final test time, scan insertion architecture planning with increased complexity at each chip generation, constrains to innovative solutions. Scan chains are still the most pads resources consuming, and hierarchical compressed IPs implemented in a hybrid flow is no longer sufficient to support the allocated pad reduction trend.
With multi-core designs, several silicon areas turn identical, and a simultaneous fault addressing is possible. The shared I/O, a new compression feature, can take advantages of such parallelization. This smart approach is able to drastically reduce the tester resources, while maintaining test quality and offering diagnosis development opportunities.
|Gate-Level DFT Flow Based on Synopsys Tool to Ease IP Reuse in Complex SOC|
Caroline Carin, Isabelle Delbaere, Emmanuel Solari, Christophe Eychenne - STMicroelectronics
With the increasing SoC complexity, IP reuse becomes mandatory to reduce significantly the time-to-market phase. But IP complexity has also progressed in parallel and for some IPs an embedded test compression can now be required to minimize scan access.
Thus, IPs have to be designed in a flexible way to support different integration based on SoC constraints and DFT tools have to support such flow:
- IP wrapper can be implemented at gate level without impacting IP RTL code (core based methodology).
- Serializer can be implemented in the SoC at gate level over IP test compression channel to re-duce scan access.
Hence, this paper describes efficient DFT gate-level flow based on Synopsys tools that improve Soft or Hard IP reuse over projects. It shares the integration experience of the same IP in 2 projects with contrasting constraints:
- Unbalanced scan chain over the design
- Small amount of DFT access at package level
|Using At-speed Testing with OCC (On Chip Clock Control)|
Bertrand Bruder, Nicolas Graffet, Vincent Chanel - Atmel Corporation, Philippe Rossant - Synopsys
The implementation and the usage of Synopsys OCC in a complex SoC using the Synopsys DFTMAX Adaptative Scan Compression technology are presented in this paper. A solution, designed at ATMEL Rousset for the SAMA5D3 product, is proposed including both the main DFT and ATPG aspects, and explaining the specificities of the design in terms of OCC Test implementation, focusing on the scan at-speed test of synchronous subsystems that run at different frequencies.
|A5 - Advanced Techniques for Multi-FPGA Prototyping|
|Prototyping a Large Multi-CPU SoC onto Multi-FPGA Boards using Certify Pin Multiplexing Techniques|
Benoit Suffran - STMicroelectronics
Large SoCs usually have wide buses and may not be partitioned into multiple FPGAs without overflowing the available IO or trace resources. Different techniques can be used to multiplex multiple signals onto the same trace and therefore decrease the need of traces between FPGA.
A simple technique is a manual implementation and integration of the multiplexing logic resulting in a modification of the SoC RTL. This manual method has a strong impact both on schedule and integration and cannot be reused across other chip developments.
Another technique is using automated ways for the implementation of the multiplexing logic, such as the Certify Pin Multiplexing tool, to add the multiplexing into the FPGAs. This technique is less intrusive and can be easily reused.
This paper gives an overview of the use of the Certify Pin Multiplexing technology on a real project and explains the modifications applied on this technology to improve the timing and solve stability issues.
|Hardware/Software Transaction-Based Verification using the HAPS UMRBus|
Frederic De Melo - CNRS
Verification of complex SoC on FPGA Based Platforms such as HAPS or ChipIt often requires to provide control on the platform from a Host PC in order to configure the hardware application, to push the data to be processed from the Host PC into the HW platform and to pull it back after it has been processed in order to check the results.
This mechanism can be implemented through transaction-based verification using the Synopsys UMRBus Communication System which allows to easily exchange data between a host PC and the dedicated HAPS hardware.
This tutorial will focus on the transactions-based verification of a partitioned design, through the UMR-bus communication, CAPIM's instantiation and specific API's generation.
Engineers and Engineering Managers responsible for ASIC/SoC verification, emulation, and prototyping
|FPGA-Based Prototyping Solution: Better, Faster, and Flexible|
Laurent Sol - Synopsys
With growing design size and complexity and a need for high performance, deciding which FPGA-based prototyping solution to choose is critical in the product development process. Do you build a custom board OR decide to try to eliminate development risk by adopting a commercial system? In this tutorial Synopsys experts in FPGA-based prototyping showcase the next generation HAPS-70 system and the key automation features that make commercial prototyping solutions attractive.
In this tutorial, you will learn how the enhanced HapsTrak 3 I/O connector technology with HSTDM delivers up to 3x performance improvement in data throughput over traditional pin multiplexing, how to accelerate multi-FPGA partitioning by up to 10x as compared to manual methods and how the modular system architecture of the HAPS-70 systems scales from 12-144 million ASIC gates to accommodate a range of design sizes, from individual IP blocks and processor sub-systems to complete SoCs.
Engineers and Engineering Managers responsible for ASIC/SoC verification, emulation, and prototyping
|A6 - Analog-Digital Co-Simulation|
|Improve IC-Level Verification Coverage by using Assertions with CustomSim-VCS Multi-Thread Real Number Flow|
François Ravatin, Sébastien Cliquennois - ST-Ericsson, Philippe Brahic - Synopsys
Time and resources to ensure a good coverage for IC-level functional verifications are growing year after year with design complexity. There is, therefore, a need to reduce simulation setup and analysis.
CustomSim-VCS with VHDL Real Number approach permits to maximize verification coverage by creating easily co-simulation setup and reuse it from one test case to another one. A stimulus using VHDL-RN methodology permits to create a sequence, controlling DUT by driving both digital and analog signals. This stimulus, using an automatic definition and selection, for both analog and digital nets permits to create assertions in order to automate IC verifications.
In addition, multicore technology implemented into CustomSim-VCS has opened new areas of verification by drastically reducing runtime.
|"Digital Supplies are Analog !" - CustomSim-VCS with UPF|
Pierre-Yves Alla - Synopsys
Many digital IPs or SoCs are now designed using UPF flows, which requires advanced low-power simulation techniques. But accurate modeling of the supplies can be complex in a digital flow, and it might make sense to use an analog supply generator. In some other cases, design teams are already using mixed-signal simulation, and would like to take advantage of UPF methodology on the digital part.
This tutorial will show how VCS Native Low Power can be used in conjunction with CustomSim, in order to create an accurate AMS + UPF simulation environment. We’ll demonstrate how to setup this flow on simple examples, presenting various use cases, and the impact on the UPF coding.
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers
|Tuesday, June 11, 2013|
1:30 PM - 3:00 PM
|B1 - Managing Constraints & Lynx Flow|
|Minimizing Risk in Multi-clock Designs with GCA1|
Eric Zann - Synopsys
Today's multi-clock designs make constraint development more difficult, and increase the risk of clock setup errors impacting your schedule. In this tutorial we will show how Galaxy Constraint Analyzer (GCA) can be used to confirm you have complete and correct constraints, and to identify structural problems in your design that impact the integrity of your clock network. During the tutorial we will explore the host of debug options available in GCA that allow you to better understand the issues identified and guide you to solutions. We’ll also look at how GCA interfaces with DC Explorer to enable constraint analysis at the earliest stages of your design flow.
|GCA -Based Methodology to Check Quality of Scan Shift Constraints|
Gianni Lazzari, Giuseppe Fornaciari - STMicroelectronics Italy, Alfredo Conte, Alberto Baldi - Synopsys Italy
This paper aims to share with the design engineers' community an efficient method to check quality of scan-shift constraints and perform exhaustive coverage analysis in single stuck-at shift scenario using Galaxy Constraints AnalyzerTM (GCA). Fundamental is to verify that boundary conditions, input/output delay settings are in line with the specs. Multiple clocks per CP pins, clock network reconvergence and unclocked CP pins belonging to scan chain elements must be avoided.
Thanks to the possibility to filter collections of a huge number of pins, we are able to analyze the list of relevant pins belonging to scan chains extracted from Tetramax using a custom procedure. The validation criteria is to: ensure 100% constrained on all scan chain element; ensure 100% constrained on all ScanOut; 0% constrained on NOT scan element; full tracing of all scan chains; 0 exceptions on scan chain element pins and on/between ATE_clocks.
The logical steps of the proposed flow will be presented in detail.
|Improve Design Quality with Efficient Design Exploration in Lynx Design System|
Riccardo Giordani - Synopsys
Today, SoC designs require unique implementation tradeoffs between power, performance and area to achieve the best results for a specific application while keeping to a tight design schedule. The solution space for finding optimal results is very large and involves multiple variables and without sufficient exploration of alternatives the optimal and most efficient implementation may be missed. In addition, late design cycle changes such as timing ECO's often require assessment of multiple possible strategies.
Using Lynx, designers can more efficiently explore the available solution space and mitigate the risks of last minute design changes. We will present how Synopsys Lynx Design System is a key productivity enabler, focusing on the following areas :
- Process and Library evaluation and comparison
- Flow and design "what if" analyses to tune the flow to the design
- Late cycle ECO execution and evaluation
Front-end and back-end design engineers, CAD engineers, flow developers and project leads
|B2 - Advanced IP Verification|
|Regression Performance Optimization of a Full HD-120fps Video Encoder Based on VCS Multi-Core Functionality|
Mikael Genay - STMicroelectronics
Verifying a Full HD video encoder is very challenging due, among others, to its infinite possibility of combinations. So in order to continuously improve the verification quality, it is required to always speed-up the simulation time. This paper describes the methodology carried out on a complex video IP to improve and optimize the full regression simulation time within a SystemC environment, based on Synopsys VCS simulator multi-core functionality, taking into account the software and hardware resources.
Simulation benchmarks will be shared.
|UVM-based Power Aware Platform for Multicore Sub-system Verification|
Massimo Calligaro - STMicroelectronics
The verification of the power architecture of a subsystem requires a specific simulation plat-form to allow execution of power scenarios. The platform element in charge of driving and collecting the power events defined in the scenarios have to be comprehensive to be able to reach all corner cases, flexible to allow randomisation of events between independent domains and based on a well-defined architecture to ensure maintainability and reuse. This paper will describe how the UVM approach has been used on a multicore subsystem to define and develop the power transaction driver and how the related events have been observed and validated using checkers and defining properties. It also provides details on how subsidiary UVM VIPs (standard and custom) have been reused and extended, on the UVM class organisation and finally on the scenarios implementation.
|Low-Power Verification using Power State Table Coverage|
Christophe Lamard, Jean Marie Guillermin - ST Microelectronics, François Cerisier, Mathieu Maisonneuve - Test and Verification Solutions, France
This paper describes low-power verification principles and the use of power state tables to identify invalid power states and power transitions. The paper will show how to use the UPF power state tables to describe valid states and transitions for verification purposes. We will then explain issues related to reset states and transitional states and show how to use the power state table coverage to identify new sequences to implement.
|B3 - Closure and Signoff|
|Using PrimeRail for Advanced Microcontroller Dynamic IRdrop Analysis|
Yann Rebours - STMicroelectronics
SoC and back-end designers need to have integrated tools in their design environment to reduce the product development time. This is particularly true at the signoff step of which the IRdrop analysis is a part. PrimeRail fits into this concept with its "in-Design" links to IC Compiler. This is why we chose to benchmark and use it for the tapeout step of a microcontroller design including split power and ground libraries and a full custom multi-voltage supply grid.
We describe in this paper how the choice of PrimeRail dynamic IRdrop analysis was made. It was based on an accurate study of the PrimeRail library characterization process using SPICE simulations as a reference. Dynamic VCD base Irdrop analysis is then presented on a chip-level design. Hot spots were identified, then reduced after supply grid fine tuning.
Some improvements of the tool are also discussed in this paper.
|IC Compiler ECO Flows for Minimal Physical Impact|
Pascal Coffin - Synopsys
With ever-increasing design complexity, a fast, convergent ECO flow is a prerequisite for today's high performance design flows. This tutorial will outline the latest IC Compiler ECO capabilities, focusing on the new Minimal Physical Impact (MPI). Also discussed will be the latest IC Compiler-PrimeTime ECO signoff flow considerations.
Experienced users of IC Compiler and PrimeTime who are familiar with existing ECO flows in both tools
|B4 - Improving Test Quality and Yield|
|Delay Faults Detection in Synchronous Clock Domain Logic|
Ravindra Babu Nayudu - Abilis Systems, Frank Nolting - Synopsys
In nanometer nodes of CMOS digital circuits, delay faults are more prevalent and can cause SoC failure in the final application. Early detection of these faults during the product life cycle is important. Late detection of a faulty device impacts the cost and quality of the end Silicon product (if not detected and binned during production test). Generating the patterns to detect these faults in intra clock domain and inter clock (synchronous) domain logic is important considering the complex SoC designs with multiple clocks (Async & synchronous) with high-speed, on-chip clocking. This paper addresses the transition fault pattern generation between synchronous clock domains using Synopsys Synchronous On-Chip Clocking mechanism to detect the faults in the logic between synchronous clocks.
|Non Scan Logic Handling in a Full Digital Design|
Cedric Escallier - STMicroelectronics
This paper presents the tricks and pitfalls to be able to manage properly "non-scan" areas in a full scan digital design. The techniques presented are related to the flow from RTL to ATPG simulations.
|Volume Diagnostics on Slack-based Transition Test Patterns to Improve Yield of a Slow Process|
Nelly Feldman, Alain Perreard - STMicroelectronics, Christophe Suzor, Salvatore Talluto - Synopsys
This paper describes the methodology used to develop optimized Slack-based Transition patterns to detect and monitor issues of slow process using volume diagnosis and statistical analysis with Static Timing Analysis (STA) results. A new 110nm technology (shrink from 130nm) had yield problems on traditional transition fault test patterns: one of the root causes was a slow process. New Slack-based Transition patterns were developed and applied on several wafers: the objective was to improve the quality of the transition patterns maintaining a good compromise between test time and test coverage. Several run of patterns generation according to Synopsys TetraMAX ATPG tool options were done in order to select the best pattern set. The data were loaded to Synopsys Yield Explorer for statistical analysis. With this approach, optimized test patterns were developed to monitor slow process and improve yield.
|B5 - FPGA-Based Prototyping Methodology|
|ASIC to FPGA RTL Prototyping using Synplify Tools|
Richard Ponizy - STMicroelectronics
Taking, as an example, the prototyping of an existing microcontroller on a "house-made" FPGA platform this presentation will cover the following points :
- The close work with the Design team in order to get a good hierarchy definition, allowing easy memories, analog modules, and clock tree identification, and treatment (replacement, specific constraints etc..)
- The description of the “house-made” prototyping platform used and the related FPGA Design flow including Synplify tools.
- Description of some good practices we have implemented in order to convert the ASIC RTL into a FPGA friendly RTL. And how successfully it have been used for this microcontroller prototyping.
It will also concentrate on the implementation step using the Synplify-tools with a special focus on:
- The conversion of Gated and Generated Clocks
- Gating/Generated clock supported/unsupported structures
- Constraint definitions using standard SDC and the usage of a successful clock conversion
- limitations, issues and workarounds
|Complex Mobile Multi-Media SoC Prototyping using Xilinx Virtex 7-based HAPS-70 Systems|
Paul Robertson - Broadcom, Andy Jolley - Synopsys
The challenge of Implementing the latest complex Mobile Multi-Media SoCs onto FPGA-based platforms for prototyping and S/W development activities has been assisted via the introduction of the latest multi-die Xilinx Virtex 7 FPGAs which have extended the individual device capacities to around the 12M ASIC gate mark which improving I/O and Core performance. This paper from Paul Robertson of Broadcom outlines the process of preapring such a complex SoC for implementation on the latest Virtex 7-based HAPS-70 Prototyping Systems from Synopsys, handling new challenges related to making best use of the multipe-die FPGAs and then bringing-up the Prototyping Systems whilst ensuring optimal system performance.
|Methodologies and Techniques for Maximizing Productivity on Large FPGA Designs|
Xavier Mathes - Synopsys
FPGA designs have become very large. As a result, the traditional top-down approach to implementation can be problematic due to long tool runtimes and the massive number of design files that must be managed. This tutorial is for designers of large FPGAs who need to reduce their overall design turnaround time and still hit aggressive performance targets. Key topics that will be discussed include: hierarchical design with a mixed top-down/bottom-up approach; techniques for incremental design; runtime improvement; and IP handling. Features to facilitate TCL scripting make it easy to search large databases, create customized reports and extract a plethora of other useful information will also be discussed. Participants in this session will learn how to take advantage of these features to achieve efficiency and enhance the design process for your FPGA designs.
FPGA Designers assembling designs that include large IPs or significant amounts of reused code, wishing to stabilize designs quickly and improve runtime
|B6 - Advanced AMS Verification|
|Aging Model Implementation using MOSRA API Flow from HSPICE to CustomSim (XA) FastSPICE: Applications at STMicroelectronics|
Florian Cacho, Vincent Huard - STMicroelectronics, Patrice Loth, Manjunatha Vadiarillat, Zhaoping Chen, Joddy Wang - Synopsys
An innovative platform of reliability simulation including all front-end wear-out mechanisms is presented. Customized physics-based models of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are implemented in MOSRA Application Programming Interface framework. Additionally, a Time Dependant Dielectric Breakdown (TDDB) checker is developed and enables to provide failure rate induced by gate oxide in overlap and channel region. Each device of the circuit is either degraded, for BTI and HCI, or a failure rate is calculated for TDDB. Result dependents on activity of each device (overshoot, activity frequency), temperature, voltage etc... The aging model is developed for an HSPICE simulator but can be extended to FastSPICE CustomSim. Aging simulation with CustomSim is a promising solution enabling the robustness assessement of a large circuit for various conditions of usage. Simulation accuracy and speed are discussed at the end.
|The Art of Reliability: Guidelines to Reduce IR-drop and Electro-Migration Effects in Full Custom Designs|
Paolo Valente, Alessandro Valerio - STMicroelectronics, Claudio Rallo - Synopsys
The design of power and signal nets is very strategic and sensitive in analog designs. The more complex the design is, the more challenging the net design and the more burdensome the verification. Considering the time necessary for parasitic extraction, verification and possible layout fixings, a dedicated flow is necessary and strategic. It would ensure not only a significant reduction in the implementation phase but also a substantial turn-around time reduction of the overall IR-drop and electro-migration reliability checks.
This paper proposes guidelines for a flow-targeted design of analog nets and describes the new key features which have been implemented in Synopsys HSIMplus tool (current reuse, static analysis, missing VIA/strap check). The innovations described are related to different phases of the design: implementation, verification and script-based design modification. Finally, the results of the key features introduced are presented as well as the further possible enhancements of the flow. The Synopsys IR-drop and electro-migration flow has been enhanced with new HSIMplus features, which have been requested and implemented to let other Synopsys users reduce the time necessary for design and verification of nets in analog design.
|Circuit Check Extension to Optimize ERC Flow, User Experience, Guidelines for Expert and Novice Users|
Alessandro Valerio, Salvatore Santapà, Pierluigi Daglio - STMicroelectronics, Carlo Borromeo, Chi-Tzung Wang - Synopsys
Static ERC (Electrical Rule Check) verification allows design weaknesses to be found earlier in the development cycle, thus reducing the cost of fixing. Fast engine and efficient algorithms are key aspects for the deployment of this methodology. On one hand, the CCK built-in commands have better performances than a solution based on TCL-CCK electrical propagation but, on the other hand, they lack control capability for violation investigation. One of the latest enhancements implemented for "sdevv" breaks the rules and opens a new era in the static electrical verification: this solution builds a real bridge between the capacity of C-commands and the flexibility of custom TCL scripts. In the reporting stage of an ERC run, ad-hoc procedures query the design database in order to classify, tag or remove the current violations. Experiments on real IPs and SoCs have been carried out. Results prove how this new built-in check extension is overall more efficient than the old approach.
|B7 - AMS Co-Design|
|IC Compiler Custom Co-Design Workshop|
This workshop gives you a hands-on experience of the features and benefits of using IC Compiler Custom Co-Design.
You will learn how IC Compiler Custom Co-Design accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.
Synopsys' Galaxy™ unified implementation solution enables design teams to easily move between digital and custom implementation flows while maintaining design data integrity. IC Compiler Custom Co-Design enables higher productivity through advanced features such as DRC/LVS-correct interactive auto-routing for shielded nets, differential pairs, matched auto-routing and automatic DRC correction technology.
IC Compiler users and CAD Engineers responsible SoC designs and SoC design flows.
|Tuesday, June 11, 2013|
3:30 PM - 5:00 PM
|C1 - Low-Power Full Flow|
|Introduction of Multi-Bit Banking Solution|
Eric Bouet - Synopsys
Optimization for power is one of the most important objectives in nanometer IC design. Reducing power consumption in chips enables better, cheaper products to be designed and power-related chip failures to be minimized. Clock trees are one of the biggest contributors to power consumption. By keeping the actual length of the clock tree short, we can immediately reduce the overall power consumption. This session will describe how IC Compiler was used to reduce the clock tree length by grouping registers together in banks of registers (the so-called multi-bit banks). By ensuring that several registers are inside one macro, the length of the clock net is reduced, resulting in power savings.
IC Compiler and DC Compiler Users who are considering usage of mult-bit registers
|Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor|
Lionel Belnet - ARM, Dale Lomelino - Synopsys
Learn how to optimize the Quad-Core ARM® Cortex™-A7 MPCore™ processor for the best power efficiency targeted for entry mobile and other power-sensitive products. This tutorial will highlight the latest technologies in Design Compiler Graphical and IC Compiler that can be used to achieve challenging power/performance targets. Shared best practices leverage Synopsys' high-performance core (HPC) methodology, including optimizations for power as a primary requirement to be managed at each step in the flow; from synthesis, placement, clock and routing, to post-route timing closure. Low power capabilities introduced here are augmented with aggressive power management of library VT classes and timing targets. The power-centric high-performance core methodology will be illustrated through a reference implementation of a quad core Cortex-A7 processor with ARM POP™ technology for core-hardening acceleration on TSMC 28HPM process. The final product is a strong starting point for designing the 'LITTLE' core in a big.LITTLE™ technology-based SoC, or as a stand-alone application processor for cost-sensitive markets.
Front-end or back-end design engineer, CAD engineer, flow developer or project lead
|C2 - Improving Debug Methodology|
|Debug Hints and Tips using Verdi3 and DVE|
Jerome Peillat - Synopsys
This tutorial gives you a hands-on experience on various debugging features and benefits using Verdi3 and DVE. You will learn how to better use the Synopsys debugging offer to speed up your debugging cycle during the verification of your subsystem or design.
and DVE, best-in-class solutions, help you enhancing your debug through:
- A better Comprehension of the design behavior
- More Automation on debug processes
- An Unification of the design/verification environments
Design and verification users and CAD Engineers responsible SoC designs and SoC design flows.
|Kalray’s Advanced Debug Flow using Synopsys Verdi and Certitude Solution |
Jehan-Philippe Barbiero - Kalray
This presentation contains a customer testimonial on various debugging scenarios using Verdi3 and chip qualification using Certitude.
Kalray's feedback will be focused on the debugging added value using the Synopsys solution, and how this debug offer helps them overcome their design and verification challenges and meet their quality objectives.
Kalray's testimonial will cover the Verdi3 customized features developed with VIA: Verdi Interoperability Apps and Certitude functional qualification.
Design and verification users and CAD Engineers responsible SoC designs and SoC design flows.
|C3 - Physical Implementation|
|Concurrent Top and Blocks Level Implementation of a High-Performance Graphics Core using One-Pass Timing Closure in Synopsys ICC|
Corine Pulvermuller, Julien Guillemain - STMicroelectronics
Implementing a High Performance Graphics Core with complex low-power features and several operating points in an advanced design node (28nm FDSOI) challenges the traditional Place and Route flow. Adding a very short schedule and improving the resource utilization for the execution of this multi-millions instances design through a Hierarchical Physical Implementation is asking for an innovative one pass timing closure flow. This article will describe how, using IC Compiler (ICC) through a top-down approach and concurrent top and blocks implementation methodology, the target frequency, the power constraints and the schedule can be achieved successfully. From the Design Planning stage to the GDSII, we will tackle the following aspects in ICC: usage of Black-Boxes for early Design Planning, Budgeting, advanced Placement and Optimization and finally close link to PrimeTime SI Signoff STA for final ECO, with specific considerations on the SDC blocks budgets and QTM models handling.
|Advanced Technologies FRAM View Generation Methodology|
Sylvain Landelle, Sophie Rabadan - STMicroelectronics, Eric Bouet - Synopsys
Traditionally abstracts were only showing functional pins as a small rectangle near their boundary. Starting with 32nm, the complexity of rules started to show real DRC issues not seen by the router because too little information was provided in the abstracts to let the router understand the rules. Two approaches can be used to overcome the problem statement: The first one introduces a lot of conservatism around the macros to avoid DRC issues. But this quickly shows limitations: too many routing resources being wasted around the macros leading to unroutable designs.
The second approach, described in this article, consists in adding more details in the abstract, to specifically show the entire metal shape of a pin and not only the top level rectangle which was traditionally shown near the boundary. This paper describes the problems with traditional abstracts, the new methodology flow and how it allows more resources to the router and avoids DRC violations.
|IC Compiler 2013.03 Release Highlights|
Oktawian Linda - Synopsys
The session will describe technologies in the 2013.03 IC Compiler release. IC Compiler's latest release delivers significant improvements in areas that remain key for physical implementation : Accelerating design closure, providing higher performance/lower power and support for advanced process nodes. Topics highlighted include enhanced Flip-Chip capabilities, complex floorplan placement, improved multivoltage flow, faster & more robust closure, Minimum Physical Impact ECO, tighter PrimeTime SI correlation and Improved In-Design physical verification.
This is an informative session that will be applicable to all IC Compiler customers
|C4 - Advanced Techniques for Test and ATPG Pattern Simulation|
|Meeting Quality Goals for Gigascale Designs: Trends and Solutions|
Alfredo Conte - Synopsys
This tutorial will highlight leading-edge capabilities in the Synopsys synthesis-based test solution for maximizing productivity, increasing test quality, and lowering test cost. First we will discuss how standards-based DFT has evolved within DFTMAX compression to save time and effort when implementing test for extremely complex designs. Next we will examine several advanced detection mechanisms in TetraMAX ATPG for improving defect coverage. Finally we will show new features in the tools that lower the cost of testing ARM processor-based designs and other multicore SoCs.
Designers and managers interested in test, quality, and manufacturing
|R&D Q&A Session - Accelerate ATPG Pattern Validation|
Slimane Boutobza - Synopsys
Increased design size and complexity and the need for higher test quality is making the ATPG pattern verification a very demanding task. This R&D Q&A session will focus on how to simplify and make more efficient and flexible the ATPG pattern verification task, giving advices on how to reduce the turnaround time. An R&D representative will be available to directly interact with the customers and talk about their challenges.
|C5 - Emulation, Transaction-Based Verification and Virtual Prototyping|
|Redefining the Emulation Landscape for the Latest SoC Challenges with Zebu Server|
Geoffroy Poquet - Synopsys
With increases in the size and complexity of today’s SoC HW and embedded SW designs, massive testbenches and tests spanning billions of cycles is becoming the norm. Meeting these challenges requires advanced verification technologies delivering the highest performance possible. The Synopsys suite of ZeBu emulation solutions are tightly integrated, best-in-class emulation technologies that deliver the best price-performance in the industy. This presentation will describe the Synopsys Zebu Emulation technology and methodology going through the different use modes, the visibility and debugging tools, Transaction-based verification and the Integration with the virtual world
Verification Engineers, Project Managers
|Fast Deployment of Zebu to Perform SW Verification & Development Before Silicon|
Stephane Haissat - Abilis, Geoffroy Poquet - Synopsys
Delivering an SoC is no longer a matter of getting working silicon on time to market; it is also a matter of developing the associated software in that time. It is vital to develop and verify the SOC SW before silicon and eventually to unveil any major system HW-SW bugs. A hardware verification platform fits perfectly this need. However, faced with the increasing number of different interfaces characterizing an SOC the challenge remains in feeding the platform with consistent data streams at a very high speed to justify the system SW verification and development cost. This paper describes how the transactional methodology combined with zebu emulators brings the abstraction level required by SW developers to build testbenches. It can handle interface scalability as well as achieving the required emulation speed. This methodology is going to be illustrated by the experience of Abilis.
|Using Virtual Prototypes for the Early Bring-Up and Test of Power Management Software|
Xavier Buisson - Synopsys
The regulation of frequencies and voltages has become a major aspect to operating system bring-up on new hardware. An analysis of complexity on recent commercial embedded application processors has shown that the drivers and configuration for the clocks and voltage regulator alone make up 50% of the device software code. In this tutorial, we will demonstrate how virtual prototypes enable the early bring-up of power-related software aspects without running into the danger of harming the hardware through overvoltage or other software defects. The tutorial will also cover the functions of major software power management frameworks within different layers of embedded software stacks. We will highlight how Virtualizer Development Kits (VDKs) are used to optimize system wide power management by simulating and analyzing power at the system level driven by real world scenario data.
Software engineers and architects concerned with low level software bring up and power management
|C6 - Advanced AMS Verification and Custom Design|
|An Accurate Path Verification to Secure and to Speed Up Nanometer Design Closure|
Salvatore Santapà, Alessandro Valerio, Pierluigi Daglio (STMicroelectronics), Andrea Barletta - Politecnico of Milan , Massimo Prando - Synopsys
When designing high-performance ICs, it is often challenging to make out whether there is still margin for improvements only relying upon information produced by Static Timing Analysis. Furthermore, at sign-off level, designers may wonder if some critical paths will eventually work also in case of different adopted conditions, in fact it is becoming necessary to shorten STA pessimistic estimations. This paper describes a validation flow able to provide a user friendly Timing/Power Path Calculation, based on real analog simulations and leveraging custom TCL procedures, to extract a back-annotated SPICE netlist from a PrimeTime run enabling to launch CustomSim simulations in order to quickly obtain accurate data. Such a timing analysis adds robustness to the design flow, thus allowing to explore design implementation and verification tasks not so easy to achieve in the frame of a pure digital flow: accurate skew measurements on wide busses, clock tree implementations driven by EMI criteria, design quotation in advanced and/or preliminary technologies, measurements outside the standard libraries domain characterization.
|Full Front-to-Back Custom Design Flow: “The Power of Custom Designer-SE & Laker" (The tutorial is followed by a Customer Testimonial)|
Guillaume Thomas, - Synopsys, Alain Vigne - BlinkSight
In this tutorial you will learn about the Synopsys custom design flow, which is based on Custom Designer SE and Laker. You'll see the complete flow from schematic entry and simulation through custom layout. In addition, you'll be exposed to several of the most advanced productivity-enhancing features of these tools.
Technologies that will be covered in this session include how data is passed between front- and back-end tools, pre- and post-layout simulation, and custom layout automation.
Schematic & Layout Designers/Engineers & CAD Managers