SNUG Boston Abstracts 

Tuesday, October 01, 2013
9:00 AM - 10:30 AM
Welcome and Introduction
Costas Conistis, Synopsys, Inc.; Chi-Foon Chan, President and co-CEO - Synopsys, Inc.
Accelerating Innovation in the Era of Electronics That Increasingly Impact Everyone, Everything, Everywhere
Chi-Foon Chan, President and co-CEO - Synopsys, Inc.

Technical innovation is increasingly impacting everyone, everything, everywhere with today’s consumers wanting it all: 24/7 connectivity, unlimited bandwidth, data, entertainment, security, portability and more. As this exponential trend continues, engineers designing the chips and systems inside of these electronics must adopt new technologies and strategies in order to deliver ever faster, lighter, smarter and cheaper products in record time. Dr. Chan’s presentation will provide insights on how to accelerate innovation in the era of electronics that increasingly impact everyone, everything, everywhere.


Tuesday, October 01, 2013
10:45 AM - 12:15 PM
A1 User Session: Performance and Regression Management
SoC Simulation Performance - Take a Second Look at Your VCS Setup
Kendall Chan - Advanced Micro Devices, Inc.
Synopsys is always developing new options to address VCS compile and simulation performance concerns. New technologies like native-low-power, multicore, partition compile, etc... tend to provide some incremental benefit but they also tend to require some commitment to support their deployment and/or development. This paper reviews a few ‘old school’ VCS methods for improving simulation performance that have been re-explored in AMD in the last few years. Synopsys VCS has always had many optional settings and methodologies that affect simulation performance that are easily overlooked by many SOC teams. Many of these can be relatively simple to deploy and provide significant benefit. Taking a fresh look at plain old VCS is always a good exercise for any SoC ASIC team.

Synopsys Tools Used:
VCS

Target Audience:
Intermediate

FPGA Continous Integration with Jenkins
Martin d’Anjou - Ciena
Continuous Integration (CI) has been recognized as one of the best agile development practices in recent years and it is fully applicable to ASIC and FPGA development. ASIC and FPGA developers have long understood the value of block level and top level verification and their impact on the success of a project. However, managing thousands of tests, hundreds of thousands of log files and coverage reports is a daunting task. This paper shows that the Synopsys tools VCS and URG are ready for Continuous Integration systems such as Jenkins. Specifically, the URG HTML reports, such as the RAL functional coverage reports, are directly digestible by Jenkins. The paper also shows that the VCS compiler log files and the simulation results can be processed and brought into Jenkins' reporting model.

Synopsys Tools Used:
VCS, URG, Ralgen

Target Audience:
Intermediate


A2 Tutorial Session: Using Concurrent Clock and Data Optimization for Improved Timing Closure
Achieving Higher Frequencies for Your Design with Early Clockgating Optimization and Comprehensive Useful Skew
Dave Power - Synopsys

This tutorial introduces new ICC features targeting higher frequencies and improved ease of use. We’ll describe enhancements to the placement and optimization of the clockgating elements prior to CTS, which deliver improved timing and convergence of the flow. The new features use improved clockgate restructuring and CTS latency estimation for more accurate clockgate placement and clock enable path timing optimization. The session will also cover new skew features in IC Compiler which use techniques including multi-stage slack borrowing and on-the-fly clock tree adjustment. These features will enable you to meet frequency goals using a simple flow, without resorting to complex multipass approaches.

Synopsys Tools Used:
IC Compiler

Target Audience:
IC Compiler users targeting high frequency solutions



A3 User & Tutorial Session: Lynx and Signoff Driven Timing Closure
I Love Lynx
Vincent Rowley - Semtech Canada Corporation

This paper discusses the benefits of the Lynx Design System in the development of mixed signals integrated circuits at Semtech Gennum Products Group.

We discuss how this RTL to GDSII design environment is leveraged across multiple projects and multi-site teams.

Some of the improvements made to the off-the-shelf flow to facilitate a PrimeTime-driven ECO flow are presented.

Synopsys Tools Used:
Lynx, Design Compiler, IC Compiler, PrimeTime, Formality, StarRC

Target Audience:
Intermediate


Signoff Driven Timing Closure with PrimeTime: Now Includes Leakage Reduction
Steve Danielson - Synopsys

PrimeTime’s 2012.12 release builds on top of Synopsys’ Galaxy low power flow and adds signoff based leakage recovery to existing ECO guidance capabilities. This tutorial will review PrimeTime’s latest enhancements to final stage ECO timing closure and how to use these capabilities together effectively. You will learn how PrimeTime’s ECO flow compliments IC Compiler’s new Minimal Physical Impact (MPI) capability to achieve fast, convergent ECOs.

Tools Used:
PrimeTime

Target Audience:
This tutorial is for all designers responsible for timing convergence and signoff.



Tuesday, October 01, 2013
1:15 PM - 2:45 PM
B1 User Session: Reuse & Low Power Verification
Test Driven Design: Unit Testing... on Steroids
Bryan Morris - Verilab

Test Driven Design (TDD) is a technique software engineers use to create their design incrementally by first creating unit tests defining the simplest functionality of the verification class or unit under test (UUT) and then incrementally adding just enough functionality to the UUT until the test passes. This process continues until the UUT has all of the required functionality.
TDD adds value into the development process by designing the usage model as the UUT is created. A side-benefit of this approach is that you also create the set of unit tests for the item being developed.
TDD frameworks exist for most software development languages. A TDD framework exists for SystemVerilog called SVUnit. Since its introduction in 2009, the framework has incrementally improved to allow TDD of verification classes, RTL, coverage properties and reporting and logging. This paper provides a tutorial to the SVUnit and TDD by creating a UVM sequence, sequencer and driver for a simplified DDR3 interface.

The end-goal of the paper is to demonstrate through a concrete example how TDD can improve the confidence in what you create and ultimately in your productivity.

Synopsys Tools Used:
VCS, UVM

Target Audience:
Intermediate


UVM-Based Vertical DV Re-use in Packet Processing ASICs
Karim Khordoc, Dennis Im, Lawrence Said - Cisco Systems

In this paper, we present our methodology for DV re-use across multiple levels of verification in packet processing systems. Such systems are characterized by a protocol stack with layered packet headers and functions such as channel aggregation, flexible channel mapping, control packet termination, packet denial, flow arbitration, and programmable header processing. These characteristics have implications on the relationships between configuration and stimulus at the block-level and on the relationships between the configuration of different blocks (e.g., compatible channel mapping and resource allocation across blocks) at higher DV integration levels. We discuss our methodology for enforcing these relationships, for building super-block level stimulus (UVM sequences) by combining block-level UVM sequences and for re-using monitors, drivers and scoreboards from block to super-block. We discuss the trade-offs in the design of the packet class inheritance hierarchy. We have deployed our methodology on a multi-billion-gate packet processing ASIC with VCS v2012.09 and UVM 1.1.

Synopsys Tools Used:
VCS, DVE and UVM

Target Audience:
Advanced


Verifying Crossover Signals in Low Power Simulation
Ashwini Holla, Andy Ray, Shu-Shia Chow - Advanced Micro Devices, Inc.

ASICs manufactured in deep submicron technologies (32nm and under) are faced with the challenge of static power being comparable to dynamic power. Such designs are power gated to allow portions of the design to shut down when not in use. In power gated ASICs, demarcation of power gated portions from the always-on blocks is very crucial to ensure proper functioning of the chip. This paper is a detailed discussion on the definition and verification needs of crossover signals. It describes the expected behavior of such signals and the consequences of violation of this behavior.  Furthermore this paper looks into how crossover signals are analyzed and verified by leveraging the Synopsys low power simulation tool (MVSIM NLP : Native Low Power).

Synopsys Tools Used:
MVSIM-Native

Target Audience:
Intermediate



B2 User & Tutorial Session: MultiSource CTS and Design Closure
The Clear Advantages of Multi-Source CTS
Sid Allman - Cisco Systems

As the relative contributions of wire delay increase in smaller geometries, there is limited reduction in clock latency as a floorplan block migrates down the technology nodes.  This increases the motivation to use multi-source CTS (M-CTS) to help reduce clock latency for manageable floorplan blocks.   This paper summarizes the clock tree generation problem experienced on several floorplan blocks at a technology node below 28nm and highlights the advantages and challenges of adopting of multi-source CTS implementation.  The results show that a significant reduction in clock latency can be achieved, but also illustrate that there are various costs and the arrival of new issues when using M-CTS.

Synopsys Tools Used:
Multi-source CTS Options

Target Audience:
Advanced


20nm Design Closure in IC Compiler Using IC Validator in-Design
Kevin Brelsford - Synopsys
A Synopsys expert will walk through how to produce 20nm routed designs in ICC that are ready for signoff.  This tutorial will demonstrate the basic auto-DRC repair capabilities, in addition to advanced features for double-patterning checking and cleanup.  In addition to DRC, we will cover the recent advances in metal fill insertion using the In-Design technology.

Synopsys Tools Used:
IC Compiler and IC Validator

Target Audience:
Physical designers interested in the areas of signoff and physical verification methods.


B3 User & Tutorial Session: Test Using IEEE 1500 and PrimeTime Multi-scenario Technology
Design Reuse and Pin Limited Test Using IEEE 1500
Vineet Joshi, Saman Adham - TSMC; Don Skinner - Synopsys

System-on-chip (SoC) design has created opportunities to reduce cost and save time by reusing or purchasing IP and integrating that IP on a current device.  Success in transporting DFT information such as pattern data and testability information has been limited so far due to a lack of EDA tools supporting core-based test standards. This paper explores the use of IEEE 1500 “Standard for Embedded Core Test” as a methodology for reusing DFT structures within a pin limited SoC. This approach will be compared with existing pin-limited test approaches such as serialized DFTMAX.

Target Audience:
Intermediate

Synopsys Tools Used:
DFT Compiler, DFTMAX, TetraMAX


PrimeTime Multi-scenario Technology
Mark Digiovanni - Synopsys

PrimeTime offers a number of technologies to accelerate both the analysis and debug of multi-scenario designs. Going beyond multi-scenario analysis, PrimeTime mode merging and simultaneous multi-voltage aware analysis (SMVA) actively work to reduce the number of separate scenarios to be analyzed. This allows users to reduce the hardware resources and turnaround time for multi-scenario analysis, while maintaining signoff quality timing correlation. Distributed Multi-Scenario Analysis (DMSA) and Interactive Multi-Scenario Analysis (IMSA) allow users to efficiently setup and debug multi-scenario runs.

This tutorial will give you the pointers you need to accelerate the timing analysis of your multi-scenario designs, while maintaining signoff accuracy. We’ll look at best practices for reducing the number of scenarios for timing analysis, and a very powerful way to achieve comprehensive analysis of multi-voltage designs. The tutorial will also offer a refresher of the fundamental DMSA/IMSA technologies to automate setup and debug of multi-scenario designs.

Synopsys Tools Used:
PrimeTime

Target Audience:
Designers and managers responsible for multi-scenario SoC and ASIC design, implementation and signoff



Tuesday, October 01, 2013
3:00 PM - 4:30 PM
C1 Tutorial Session: UVM Verification IP Reuse and Debug
Leveraging UVM and Discovery VIP for Better and Faster Verification
Jason Chen, Navdeep Singh - Synopsys

In this tutorial we will learn how to leverage a Synopsys Discovery VIP to meet the verification requirements for a DUT from sequence development to verification planning. Customization of sequences and testbench environments using advanced UVM factory and callback methods will be discussed. We will also learn how to debug the stimulus using the Protocol Analyzer as well as some planning and interactive testbench debug capabilities in DVE for UVM and constraint related issues.P>

Synopsys Tools Used:
VCS, DVE Protocol Analyzer, VIP

Target Audience:
This session will be applicable for Design Verification Engineers and anyone working with VCS, DVE, and or Verification IP.



C2 Tutorial Session: IC Compiler ECO Flow For Minimum Physical Impact (MPI)
IC Compiler ECO Flows for Minimal Physical Impact
Neil Moore - Synopsys
With ever-increasing design complexity, a fast, convergent ECO flow is a prerequisite for today’s high performance design flows. This tutorial will outline the latest IC Compiler ECO capabilities, focusing on the new Minimal Physical Impact (MPI). Also discussed will be the latest IC Compiler-PrimeTime ECO signoff flow considerations.

Synopsys Tools Used:
IC Compiler, PrimeTime

Target Audience:
Experienced users of IC Compiler and PrimeTime who are familiar with existing ECO flows in both tools


C3 User & Tutorial Session: Power Aware ATPG and Formality ECO
Power Aware Automatic Test Pattern Generation for ASIC Using TetraMAX
Nirav Nanavati, Miteshwar Patel - eInfochips

Design For Testability (DFT) and low power issues are very much related to each other.  Test power is equally important as functional power as we move towards miniature CMOS circuits. Power aware ATPG and a complete implementation flow is discussed in this paper, along with several power aware automatic test pattern generation (ATPG) experiments that were done to reduce power during testing.

Synopsys Tools Used:
TetraMAX, VCS

Target Audience:
Intermediate


Speeding ECO Implementation and Verification with Formality Ultra
Steve Lamb - Synopsys

This tutorial will explore a new set of capabilities available in Formality Ultra designed to help the designer speed the functional ECO implementation and verification process.  Formality Ultra helps to pinpoint where the ECO needs to be made, allows the designer to edit and view the changes in the Formality environment, allows for quick verification of the ECO’d portion of the design, then produces an ICC compatible ECO script.

Synopsys Tools Used:
Formality

Target Audience:
IC design engineers and managers who want to learn new techniques to improve productivity and predictability during the functional ECO flow.



Publish Only
Estimating Load Torque and Moment of Inertia in an Electric Motor Drive System
Novica Losic - Honeywell
A comparison between conventional and an improved modeling scheme for determining load torque or system moment of inertia for an electric machine in motoring mode is presented.

Analysis of Active Boost vs. Passive Power Conversion in Variable Frequency Aerospace Applications
Novica Losic - Honeywell
A comparison between active boost and passive AC-DC power conversion in variable frequency aerospace applications has been addressed using Synopsys tools. Power quality figures in the two approaches have been obtained and performance results against the industry governing standards have been presented.

An Efficient Way to Insert Test-Points at Analog Hard Macro I/Os
Howard Lu - Semtech Corp.

In order to improve testability for a Mixed-Signal ASIC, we normally insert Test-Points at analog Hard-Marco I/Os.  For an Analog Hard-Macro with N inputs and M outputs, to insert Test-Points on all the I/Os at the Hard-Macro will usually require (N+M) scan flops. For a very congested design with many instances of analog Hard-Macros and each Hard-Macro having considerable number of I/Os, the amount of scan flops for the Test-Points can be significant.

An efficient way is discussed in this paper to save the number of scan flops for the Test-Point insertion. The test-Point insertion methodology presented in this paper can reduce the number of scan flops by 50% or more without significant impact on test coverage in many cases.