SNUG Boston Abstracts 

Thursday, September 12, 2013
9:15 AM - 10:30 AM
Welcome and Introduction
Jay Wasserman, SNUG Boston Technical Chair - Analog Device Inc., Aart de Geus, Chairman and co-CEO - Synopsys, Inc.
Massive Innovation and Collaboration into the "GigaScale" Age!
Aart de Geus, Chairman and co-CEO - Synopsys, Inc.

The semiconductor industry is on the bridge to a new world of complexity empowered by smaller dimensions, new transistor types, enormous IP reuse, and a focus on the great potential of electronic systems. In other words, the GigaScale Age is upon us!

In addition, our customers are facing uncertain markets where merely making a better version of their last product is not sufficient. To survive and thrive in new and unknown markets, designers and their ecosystem partners are accelerating both their innovation and their collaboration with key partners. They expect the same from their EDA, IP and services partners.

In his presentation, Aart will give an overview of the enormous amount of recent innovation and collaboration happening at Synopsys as we enable "Moore’s Law plus, plus" for yet another decade!


Thursday, September 12, 2013
10:45 AM - 12:15 PM
A1 User Paper Session - Advanced Verification Techniques
Managing Verification of Highly Parameterized Designs
Joe Manzella, Rich Peachey - LSI
Industry trends are to re-use design IP in multiple projects. Parameterized RTL modules are often used to allow customization of the IP without recoding. As a natural extension of this philosophy, verification IP may be parameterized. While some benefit can be gained by using this approach, maintaining highly parameterized VIP quickly can become cumbersome, especially when dealing with parameterized base classes and parameterized interface classes.

This paper will explore some of the pitfalls of using parameters in SystemVerilog classes, and some lessons that have been learned along the way. We will also consider some alternate approaches that yield similar results, with far less complexity in the verification library.

Synopsys Tools Used:
VCS, VMM

Target Audience
:
Intermediate

Who's Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification Environment
David Brownell - Analog Devices, Inc.
With the adoption of SystemVerilog and UVM the size and complexity of testbench code has increased dramatically over the years to the point where the testbench code often dwarfs the size of the RTL design code to be verified. Along the way it was recognized that bugs in the testbench code are as dangerous as bugs in the RTL and that a method to objectively measure the quality of the entire verification environment was required.

The traditional methods of Code and Functional Coverage were a good start, providing insight into the stimulus capabilities of testbenches, but these metrics provide no visibility into whether the scripts, tests, and checkers that make up the whole verification environment are capable of detecting bugs if they exist in the RTL. Functional Qualification tools are intended to fill this gap.

This paper will describe how we have successfully used one such tool, Synopsys Certitude, to fill this void in our verification signoff process. Topics covered will include integrating Functional Qualification into different verification environments, running the tool, analyzing results, and examples of real issues found in our verification environments.

Synopsys Tools Used:
Certitude/VCS

Target Audience:
Introductory


B1 Tutorial Session - Advanced FPGA Implementation
Designing with Xilinx 7 Series FPGAs
Steve Gercken - Synopsys
This tutorial is for FPGA designers targeting Xilinx 7 Series FPGAs (Virtex-7, Kintex-7, Artix-7 and Zynq) using Synplify synthesis and Vivado place & route. You will learn how to easily run Vivado via the Synopsys provided TCL scripting templates as well as how to drive synthesis and place and route to achieve maximum efficiency and quality of results for your 7 Series designs. Key topics that will be discussed include constraints setup, forward annotation of information to place & route, and IP handling. The tutorial is designed to provide practical knowledge that may be used right away on 7 Series FPGAs.

Integrating Custom Logic in SoC FPGAs
Andy Lee - Arrow/Altera Corporation
With the proliferation of System On Chip FPGAs, engineers face challenges in integrating custom logic into these designs.  Altera's Qsys System Integration Platform builds hard processor systems in FPGA's but what about custom logic and peripherals?  What is the best way to integrate custom logic into an SoC system?  This paper examines methodologies for integrating logic from a top level hdl file and integrating custom logic through Qsys


C1 User Paper & Tutorial Session - Frontend Implementation - Multi-Voltage Design Verification and Formality Ultra
Successful Multi-Voltage Design: Using Power-aware Equivalence Checking and Static MV Analysis to Boost Tape-out Confidence
Conor Byrne, Padraig Golden, Venkatesh Jakke - Intel
Multi-Voltage (MV) design driven by the IEEE 1801-2009 (UPF2.0) standard introduces new verification complexities which traditional EDA verification tools cannot fully address. This paper, based on the experience of a successfully taped out MV SoC, describes how static MV checking and the latest power-state aware equivalence checking functionality complement and augment existing verification methodologies. The result is the ability to tape out a MV design with a very high degree of confidence.

Advanced Debugging Features of Formality Ultra
Steve Lamb - Synopsys
This tutorial will explore a new set of capabilities available in Formality Ultra designed to help the designer shorten the functional ECO implementation and verification process. Formality Ultra helps to pinpoint where the ECO needs to be made, allows the designer to edit and view the changes in the Formality environment, allows for quick verification of the ECO’d portion of the design, then produces an ICC compatible ECO script.


D1 User Paper & Tutorial Session - Plug In and Sign Off - Physical Verification Within IC Compiler
Conquering First 20nm Tapeout Challenges with IC Compiler and IC Validator
Scott McCloskey - Qualcomm; Amzie Adams - Synopsys
Migrating from 28nm to 20nm presents unprecedented  challenges.  The introduction of double patterning (DPT) and the associated order of magnitude increase in design rule complexity triggers an avalanche of unique problems that must be addressed.  DPT is a game-changer, impacting library cell design, placement, optimization, timing closure and of course routing.  Taping out your first 20nm design while simultaneously breaking in new libraries is even more difficult.  This paper will describe how ICC and ICV were successfully deployed to overcome all challenges and still meet an extremely tight schedule.
 
Synopsys Tools Used:
IC Compiler and IC Validator
 
Target Audience:
Intermediate

20nm Design Closure in ICC using IC Validator in-Design
Chris Grossmann- Synopsys
A Synopsys expert will walk through how to produce 20nm routed designs in ICC that are ready for signoff. This tutorial will demonstrate the basic auto-DRC repair capabilities, in addition to advanced features for double-patterning checking and cleanup. In addition to DRC, we will cover the recent advances in metal fill insertion using the In-Design technology.

Synopsys Tools Used:
IC Compiler and IC Validator

Target Audience:
Physical designers interested in the areas of signoff and physical verification methods.


E1 User Paper & Tutorial Session - Advanced Test Techniques
Placement Based Analysis of Scan Test ATPG Results
Glenn Boyer - Synopsys, Kelvin Ge - Samsung
Analyzing and controlling power during scan based testing is an integral part of the ATPG process at Samsung. TetraMAX ATPG employs specialized algorithms to control the switching activity caused by the test patterns it generates . Several papers on the TetraMAX power-aware capabilities have been published that demonstrate the basic tool features as well as the correlation between switching activity and actual power measurements . In this paper we will propose a new methodology for analyzing ATPG switching activity by combining physical placement information with hierarchical switching activity data to create a physical switching activity plot. We will also convert the plot to a heat map which enables quick identification of potential ATPG switching activity ‘hot spots’. Both the physical and logical info revealed from the ‘hot spots’ will be invaluable data for further analyzing the power related failures, e.g. IR Droop, issues on devices under test. Future analysis areas that leverage these new methodologies will also be identified. The results presented will be on a 28nm ARM® Cortex-A15 quad-core design.

Synopsys Tools Used:
TetraMAX

Target Audience
:
Advanced

Meeting Quality Goals for Gigascale Designs: Trends and Solutions (Part 1)
Mona Marmash - Synopsys
This tutorial will highlight leading-edge capabilities in the Synopsys synthesis-based test solution for maximizing productivity, increasing test quality, and lowering test cost. First, we will discuss how standards-based DFT has evolved within DFTMAX compression to save time and effort when implementing test for extremely complex designs. Next, we will examine several advanced detection mechanisms in TetraMAX ATPG for improving defect coverage. Finally we will show new features in the tools that lower the cost of testing ARM processor-based designs and other multicore SoCs.

Synopsys Tools Used:
DFTMAX, TetraMAX

Target Audience:
Designers and managers interested in test, quality, and manufacturing.


F1 User Paper & Tutorial Session - Transistor-level Static Timing
Accurate Timing of Dynamic Circuits Using NanoTime Static Timing Analysis
Meghna Singha, Timothy Correia, Yaping Zhan, Stephen Lim, David Newmark - Advanced Micro Devices; Norb Heindl, Paul Collins - Synopsys
Dynamic circuits require precise timing to ensure proper functionality and avoid optimistic timing results. There are three relevant components to timing dynamic circuits to ensure correctness: precharge timing, keeper timing, and evaluate timing. The challenge is to design the interactions among the three for optimum timing and power. This paper describes how we defined a specification that included native NanoTime dynamic checks and created additional checks using existing NanoTime commands. The challenges were to ensure that the asserting and de-asserting paths came from the common clock because of the exclusive nature of the inputs and the use of pushouts in cases of overlap between the evaluate and precharge nets. In this paper, we will discuss how we used NanoTime to create comprehensive dynamic checks and the new features that were added to support them.

Synopsys Tools Used:
NanoTime

Target Audience:
Advanced

Differential Full-swing Static Timing Analysis Enhancements to NanoTime
Maureen Ladd, Synopsys
Full-swing differential circuitry is a common technique employed in Serdes and similar designs and requires more complex static timing analysis verification.  Starting with the H-2013.06 release, NanoTime Ultra supports static timing analysis of these types of full-swing differential circuits, expanding the coverage of transistor-level verification. This tutorial will introduce the support, provide examples, and describe ongoing enhancements, enabling the user to quickly access these new features.


Thursday, September 12, 2013
1:15 PM - 3:15 PM
A2 User Paper & Tutorial Session - Coverage Closure and other Verification Topics
Covering the Gap: A Tutorial on Coverage-Driven Verification Methodology
Kurt Schwartz - Willamette HDL, Inc.
Advanced tools and technology such as constrained randomization, coverage, assertions, and OOP libraries are necessary to verify modern SoC IPs, but they are not sufficient. A good methodology is critical to verification success.  This paper describes a coverage-driven methodology that is being successfully used to verify very large, state-of-the- art SoC IP blocks.  We'll discuss the entire process from the initial high-level planning sessions, to the development of the verification environment structure, all the way to the implementation of low-level assertions and coverpoints.  Along the way, we'll point out what works well, and what to avoid.  Think of this paper as a tutorial on coverage-driven verification methodology, along with worked examples drawn from a real-life project.
 
Synopsys Tools Used:
VCS, hvp
 
Target Audience:
Introductory

Making the Most of SystemVerilog and UVM - Hints and Tips for New Users
Dr. Christopher Suehnel, Dr. David Long - Doulos
In the two years since UVM 1.0 was released by Accellera, UVM has become the new standard verification environment for many companies. However, engineers often find that the size and complexity of the SystemVerilog language and the UVM class library make it hard to learn how to make effective use of their many features. This paper is intended to give guidance to engineers about some useful features of both SystemVerilog and UVM that are often overlooked, used incorrectly or simply avoided because they are perceived as being too hard to understand. The first part identifies the most common novice-user mistakes and sets out rules to avoid them. The second part discusses useful enhancements to verification capabilities that can be obtained from a deeper understanding of several SystemVerilog and UVM features. It provides simple examples and guidelines to show how each enhancement can be achieved.

Synopsys Tools Used:
VCS, DVE

Target Audience:
Introductory

Coverage Closure and Debug Using Symbolic Simulation
Courtney Schmitt - Analog Devices, Inc.; Manoharan Vellingiri, Alex Wakefield - Synopsys
Closing coverage in a constrained random methodology is a challenging problem that takes a significant portion of the development schedule. There are two distinct tasks that make coverage closure difficult: finding test and seed pairs to hit reachable points and debugging why a coverage hole is unreachable.

ADI partnered with Synopsys to deploy some advanced technology that uses symbolic-simulation in addition to the regular event-based simulation to assist in our coverage closure. This technology runs a value (event) based simulation in parallel with a symbolic (equation) based simulation, and then solves the resulting equations to provide reachability information.

The tool can automatically generate directed tests to hit reachable coverage points. It also provides actionable debug information for the unreachable holes by showing the lines of code preventing the hole from being filled.

The technology is applicable to functional, code, and assertion coverage, and assisted us in the significant task of coverage closure for our design.

Synopsys Tools Used:
New symbolic simulation tool (pre-release)

Target Audience:
Intermediate


B2 Tutorial Session - FPGA Prototyping and Verification
Formal Verification of FPGAs
Gene Stuckey - Synopsys
The increase in size and complexity of FPGA designs has caused design verification to become more critical in the design process. While simulation and prototyping are still the norm for verifying design functionality, formal verification methods have become invaluable in tracking down implementation issues. This tutorial will cover the methods of using Synopsys Formality equivalence checking solution to verify results from the Synplify Premier FPGA synthesis tool.

Verifying Low Power ASIC Design Specification (UPF) via FPGA Prototyping
Carl Cleaver - Synopsys
Low power design specifications for ASIC design can be captured using the standard IEEE 1801-2009 Unified Power Format (UPF). This format specifies details for low power techniques such as isolation, retention and power management connections. As a means to verify the functionality of those techniques in hardware, Synplify Premier can process the ASIC UPF file and implement the requirements in an FPGA Prototype.

Using FPGA-based Prototyping Systems for M-PCIe System Development
Peter Calabrese - Synopsys
Using the new M-PCIe (Mobile Express) ECN to the PCI Express specification as a case study, this tutorial will show how FPGA-based prototyping can reduce design risks and enable early functional systems. It will outline key issues that designers face when integrating new protocol standards in their SoCs, and the effect of prototyping on mitigating those risks. The tutorial will present the Synopsys FPGA-based prototyping platforms and tools as well as how the tools were used to develop two of the world’s first M-PCIe systems.

Synopsys Tools Used:
HAPS, Synplify Premier

Target Audience:
FPGA/ASIC designers and verification engineers


C2 User Paper & Tutorial Session - Frontend Implementation: Optimization
Applying DOE to Logic Synthesis and Placement
Ethan Bancala - Advanced Micro Devices
In using automated logic synthesis and placement tools, designers often modify input parameters in hopes of obtaining a higher-quality design. Because exhaustively testing all possible input configurations is inefficient and costly, designers often overlook potentially optimal solutions or try overlapping experiments that may be unnecessary.

Alternatively, given a set of important parameters and a maximum number of experiments that can be conducted, design of experiments (DOE) can be used to intelligently choose a sub-set of experiments to run from the exhaustive set while learning as much as possible about how the tested parameters affect design quality. The results then can be fed into a statistics tool to determine which parameters are strongly correlated with design improvements and predict the optimal set of parameters.

Synopsys Tools Used:
Design Compiler, IC Compiler, PrimeTime, and PrimeTime PX

Target Audience:
Advanced

DC Graphical Layer Optimization
Chris Kennedy - Synopsys
As process nodes continue to shrink, the physical dimensions of routing layers become less uniform.  New Design Compiler features allow users to promote timing-critical nets to upper routing layers that possess favorable unit parasitics.  This tutorial will highlight some of the currently available methods to assign nets to specific layers, from manual assignments with net search patterns to automatic assignments with the compile_ultra -spg -layer_optimization options.  The pros and cons of each usage model will be discussed, as well as future development plans for this emerging technology.

What's New in Synthesis from R&D's Perspective
Janet Olson - Synopsys
Advances in process node, design complexity, and the need for faster performance and/or smaller designs have driven the need for new technologies in Design Compiler. Recent releases of Design Compiler provide new functionality for physically aware multi-bit, clock gating, and other technologies to improve power, area, timing and productivity. Get a preview of how you can analyze your design early-on and cross-probe back to RTL to improve your RTL quality for a faster implementation. Design Compiler R&D will talk about these technologies to show what is new in Synthesis.

Synopsys Tools Used:
Design Compiler

Target Audience:
IC design engineers and managers who want to learn the latest capabilities to improve productivity and predictability - mainstream or advanced users.


D2 Tutorial & User Paper Session - Taking Your Design Skills to the Next Level
Multisource CTS: Achieve Higher Frequencies for Your Design
Dave Power - Synopsys
This tutorial introduces an ICC feature targeting higher frequency designs. We will discuss the multi-source clock tree methodology which provides an alternate structure to implement high speed clock trees. This feature will help you to meet frequency goals using a simple flow, without resorting to complex, alternative approaches.

Synopsys Tools Used:
IC Compiler

Target Audience:
IC Compiler users targeting high frequency solutions.

Application of the Multisource CTS Operative in IC Compiler
Ryan Helfand - Advanced Micro Devices
The IC Compiler-based, Multisource CTS flow is a streamlined and effective means to accommodate clock sinks spread across the floorplan of large designs. This CTS flow offers a valuable compromise between the standard clock mesh and traditional clock tree synthesis approaches to clock distribution. The resultant networks exhibit improved QOR compared to vanilla CTS-based trees built from singular clock roots.

The flow enables convenient distribution of sinks among clock roots not explicitly described in the RTL, thus eliminating the need to alter that RTL to service implementation-level CTS needs. Furthermore, the flow provides ease and flexibility in the determination of the optimal number of roots that should interact with the redistribution layer (RDL) responsible for source clock-transmission. This paper will present the exact approaches, along with associated results. Discussion will include relevant observations and suggestions for future improvements to the flow.

Synopsys Tools Used:
IC Compiler

Target Audience:
Introductory

Engineering Trade-Offs in the Implementation of a High-Performance Dual-core ARM® Cortex™-A15 Processor
Barry Spotts - ARM®, Darin Hauer - Synopsys
Learn about the engineering trade-offs and flow development process to balance gigahertz+ performance and low power on a dual-core Cortex-A15 MPCore™ processor implementation. This tutorial will highlight best practices and technologies from the Galaxy Implementation Platform to meet challenging performance targets, while minimizing leakage power. Synopsys' high-performance core (HPC) methodology will be demonstrated through a reference implementation of a dual-core ARM® Cortex™-A15 processor with ARM® POP™ technology for core-hardening acceleration on TSMC 28HPM process. Technologies featured include physical guidance for a predictable implementation flow, transparent interface optimization for faster top-level closure, and final-stage leakage recovery for reduced leakage power. A special section will present the multi-source clock and useful skew technologies used in high-performance cores.

Employing Data Flow Analysis Techniques
Tom Concannon - Synopsys
Implementing designs with a large number of macros and other challenging floorplan parameters requires physical designers to be more aware of the data flow of a design rather than the fine details of cell interconnect. The new Data Flow Analysis (DFA) technology enables physical designers to bridge the gap between RTL and physical design in order to better understand the design and refine macro placement. This demo will show you how to utilize the new DFA features that are within IC Compiler, but also accessible from within Design Compiler via the ICC-DP interface.

Synopsys Tools Used:
IC Compiler, IC Compiler-DP

Target Audience:
IC Compiler and Design Compiler users with a knowledge of basic floorplanning tasks.


E2 Tutorial Session - Improving Test
Meeting Quality Goals for Gigascale Designs: Trends and Solutions (Part 2)
Tim Yuan - Synopsys
This tutorial will highlight leading-edge capabilities in the Synopsys synthesis-based test solution for maximizing productivity, increasing test quality, and lowering test cost. First, we will discuss how standards-based DFT has evolved within DFTMAX compression to save time and effort when implementing test for extremely complex designs. Next, we will examine several advanced detection mechanisms in TetraMAX ATPG for improving defect coverage. Finally we will show new features in the tools that lower the cost of testing ARM® processor-based designs and other multicore SoCs.

Synopsys Tools Used:
DFTMAX, TetraMAX

Target Audience:
Designers and managers interested in test, quality, and manufacturing.

Debugging Low Test Coverage
Mona Marmash - Synopsys
Often a specification, or at least a design goal, is to achieve high test coverage. So how does one debug low coverage, or better, how does one know if the design will have low coverage early on? This tutorial reviews debugging techniques to identify the cause of low coverage both within TetraMAX and early in the design flow during DFT synthesis. Because functional timing exceptions impact at-speed test coverage, we will also discuss the automation between STA and ATPG.

Synopsys Tools Used:
DFTMAX, TetraMAX & PrimeTime

Target Audience:
Front end and Test engineers.


F2 User Paper & Tutorial Session - Custom Design and Layout
Corner Wiring and Via Placement Made Easy in Custom Designer Layout Editor
James Cherry - Kapik Inc.
Kapik have augmented the Custom Designer layout editor with two new menu options: one that greatly simplifies adding a dense grid of vias to connect two or more metal layers where they cross; the other that automatically places one or more polygons to connect one or more pairs of metal lines near the corner of a layout. The two options can be used together to rapidly connect power bus lines (or, indeed, signal lines) that run around the edges of a layout. The placed polygons need not be pure Manhattan. The user can control how much of a 45 degree segment is generated. Moreover, the via-to-via spacing and via-to-metal-edge distance are user-controlled, per via layer (M5 M4, M4 M3,etc.) Where possible, vias are not placed individually. They are arrayed vertically, which hugely reduces the number of placed instances

Synopsys Tools Used:
Custom Designer layout editor, Tcl API calls

Target Audience:
Introductory

Laker3 Custom Layout System - " An Advanced Process Node Layout Tutorial"
Janet Talamentez - Synopsys
In this technology session you will learn how Laker, with its unique automation and advanced capabilities, offers ideal solutions for those seeking to improve layout productivity in addition to those who are faced with advanced technology layout challenges introduced by 20nm and 16nm technology nodes. You will see how Laker’s Custom IC Solutions for Analog and Mixed Signal Designs will help improve productivity, usability and quickly get to layout which is DRC and LVS correct. Technologies covered in this tutorial include Laker's rule-based layout, schematic-driven layout, and pattern-based multi-device layout features - which have been updated for process nodes at 20 nanometers and below.


Thursday, September 12, 2013
3:30 PM - 5:00 PM
A3 User Paper Session - UVM Based Verification Techniques
Considerations for Development and Support of Exportable UVM IP
Steven K. Sherman – Advanced Micro Devices
UVM IP intended for export to other testbenches should carefully adhere to guidelines and best practices to avoid costly usage and maintenance issues. This paper discusses some of those considerations in practice within our verification group at AMD including special considerations with respect to adoption of UVM.

Synopsys Tools Used:
VCS and related UVM support

Target Audience:
Intermediate

Getting Around the UVM "One Test-top Approach"
Anshul Dhingra, Nithin Nagar Dhruvanarayan, Dave Workman - Advanced Micro Devices
UVM (and OVM before it) are frequently presented as a single over-arching testbench environment with one ‘test top’.  Yet development of individual IP testbenches creates integration headaches when this one ‘test top’ approach is followed.  What if we have multiple instances of the top level DUT at the SoC? The problem on hand is to seamlessly merge other verification components (OVM/UVM) with your IP testbench at the top without the need of manual stitching of verification components. We did not want to add `ifdef conditional code, and yet despite searching on-line we found no specific solutions. So, after some trial-and-error, we found that the testbench components can be instantiated in a module or an interface which in turn is bound to the DUT using the “bind” construct.
 
Synopsys Tools Used:
VCS, DVE, UVM
 
Target Audience:
Intermediate


B3 Tutorial Session - System Implementation and Verification
Application-Specific Processor Design and Prototyping
Drew Taussig - Synopsys
What if you could combine performance and power efficiency of dedicated logic with the programmability of a processor? Application-specific processors (ASIPs) tailored to the domain-specific requirements bridge this gap, and are applied to a wide range of applications spanning communication, image processing, sensor systems and industry automation.
This tutorial will explain when and why ASIPs can be an alternative, demonstrating how to design an ASIP and automatically generate RTL as well as all of the software development tools from a single LISA description. This enables rapid exploration and implementation of different processor architectures. Using the HAPS FPGA-based prototyping system, we will demonstrate how the generated RTL can be integrated into an FPGA-based prototype with a complete integration of the software debug environment on top of the FPGA solution.

Complex SoC Prototyping Using Xilinx Virtex-7-Based HAPS-70 Systems
Andy Jolley - Synopsys
The challenge of implementing the latest complex mobile multimedia SoCs onto FPGA-based platforms for prototyping and software development activities has been assisted via the introduction of the latest multiple-die Xilinx(r)Virtex(r)-7 FPGAs. These FPGAs have extended the individual device capacities to around the 12M ASIC gate mark, which improves I/O and core performance. This tutorial describes the process of preparing such a complex SoC for implementation on the Xilinx Virtex7-based HAPS-70 prototyping systems from Synopsys, handling new challenges related to making the best use of the multiple-die FPGAs, and then bringing up the prototyping systems while ensuring optimal system performance.

Synopsys Tools Used:
Synplify Premier, HAPS

Target Audience:
Engineers and Engineering Managers responsible for ASIC/SoC verification, emulation, and prototyping.


C3 Tutorial Session - Frontend Implementation: Test & Low Power
Test it, Test it, You Want to Test it!
Dave Chagnon - Synopsys
Today's integrated circuits are increasingly complex. Given manufacturability requirements, circuit testability is a mandate. This means that test must be considered equally with other requirements like function, timing, area and power. Iterations due to test must be eliminated at the earliest stage of the design. RTL designers and DFT engineers need to work closely to avoid pitfalls that could compromise manufacturability. This presentation gives insights on how to design "test-friendly" RTL. How to check RTL for DFT rules is discussed, and synthesis guidelines are provided.

How Low Power Can You Go?
John Geremia - Synopsys
Today, power concerns are everywhere and low power design has transitioned from a nice-to-have to an absolute must-have. In this tutorial, we will discuss current and near term future capabilities of Design Compiler with regard to satisfying these low power requirements. Topics to be included are: Synthesis methodologies for the low power designer; improved leakage optimization capabilities; and a review of the tried and true dynamic power optimization technique of clock gating. Plan to be at this presentation and be cool.


D3 Place and Route Vision Session
Advances in Place and Route Technology
Michael Jackson, Vice President of Engineering and Lead Technologists - Synopsys
Even though IC designers around the world have made IC Compiler the clear leader for place-and-route, user feedback tells us there is still more we could do to ease the burden of the Physical Design engineer. Perpetually increasing chip complexity, shrinking market-introduction windows and ever-increasing demands on performance make Physical Design one of the most challenging tasks for an IC design house. In this session, Synopsys Vice President of Engineering Michael Jackson and key technologists will present the Synopsys vision for what it is going to take to meet these challenges.


E3 User Paper & Tutorial Session - Static Timing
Timing Verification for CDC Paths in Large-scale SoCs
Sambasivan Narayan, Michael Tresidder - Advanced Micro Devices
Signals undergoing asynchronous transfers and crossing clock-domain boundaries are typically flagged and checked with static tools at the register-transfer or gate level. The conventional methodology of false-pathing these signals during the implementation and STA stages potentially violates certain temporal assumptions associated with these crossings that need to be met to produce an error-free design. Manually verifying these assumptions is not a scalable approach for a large SoC with millions of such signals. In this paper, we detail our methodology of embedding these timing assumptions into the RTL, which allows the timing requirements to be verified during functional simulation and carried forward into the implementation and STA stages, and focus on our approach to timing these paths efficiently using virtual clocks in PrimeTime for very large SoC designs.
 
Synopsys Tools Used:
PrimeTime
 
Target Audience:
Advanced

PrimeTime Advance Topics and Flows
Bob Grozier - Synopsys
This session covers the new technologies in PrimeTime to meet the demand for faster turnaround time in timing closure for ECO and sign-off design flows. We’ll introduce you to the latest advances in performance and capacity, as well as signoff enhancements including technology for scenario reduction, enhanced constraint analysis, ECO enhancements to add leakage recovery and further improve timing fix rates, and new margining methodology to improve runtime while maximizing accuracy and productivity. in gigascale and gigahertz design flows


F3 Tutorial Session - FinFET Transistor-level Extraction and Simulation
StarRC Transistor-level Extraction: Optimizing Accuracy and Performance for Custom AMS Flows and sub-20nm Technologies
Synopsys
Highly-accurate transistor-level extraction is critical not only for device and IP characterization, but also for verifying design robustness in areas like reliability, ESD failures, and timing analysis. This tutorial provides an update on how the recent release of StarRC has improved overall transistor-level accuracy to ensure design integrity. Also described are best practices for performing extraction with StarRC to optimize performance and improve productivity and the user experience. The tutorial concludes with information on how StarRC handles the challenges that advanced geometries have introduced, such as trench contacts, FinFETs, and double patterning.

BSIM-CMG FinFET Model Complexity and its Impact on Synopsys AMS Simulation
Bob Williams - Synopsys
Process technology innovations have fueled the increasing density, performance, and power demands made of today’s sophisticated SoCs. The adoption of FinFET transistor structures at geometries below 20nm affirms the commitment by semiconductor foundries to the continuation of Moore’s Law.  The complexity of FinFET technology poses many technical challenges, particularly in the areas of transistor modeling, extraction and simulation. This presentation discusses the fundamentals of FinFET technology along with the modeling requirements, and the impact on transistor-level simulation that needs to be managed to preserve the AMS designer’s analysis TAT and productivity.


Publish Only
Verifying Full Node Traversal With NanoTime
Dan Hartman, Vasu Kandadi - Cavium Networks
Static timing analysis is generally very powerful for getting the worst-case timing paths through a block, but when path tracing does not go through a particular piece of logic it can be difficult to detect. One can leverage NanoTime's internal database to show that which nodes that were never analyzed, even when path pruning is enabled. Further techniques will be shown to refine the data so false-path and other exceptions do not generate excessive data for the user to review.

Automated Testbench for Coverage Closure
Anshul Dhingra, Dave Workman, Nithin Nagar - Advanced Micro Devices
Processors are complex and multiple HVL's are used to verify various components of the design. Running regression suites against the design can take up to several months to complete. It is because each test is running hundreds of thousand instructions which consume lot of time. So eventually even after hours of functional simulation, UVM based sequencers are not able to gen-erate enough stimulus to cover all cross feature scenario. We propose a technique effective at sys-tem level verification that automates the test generation to achieve coverage goal for UVM based drivers in limited time and compute slots. This is accomplished by analyzing the achieved cover-age from the existing tests and input coverage file. Algorithm chooses a random value from set of values defined in coverage file, continuing to target random space. Command line arguments are processed by the UVM command line processor which modifies the random constraints to generate a desired scenario.

SDMLp Standard Cell Library Generation using Synopsys Custom Designer, Liberty NCX & Milkyway Tools
Antarpreet Singh Manchanda, Mike Borowczak, Dr.Ranga Vemuri - University of Cincinnati
As information processing moves at a fast pace to small portable embedded devices, the information channels and endpoints need greater protection. In the last decade, a new class of side channel attacks became public called Differential Power Attacks(DPA). These attacks exploit power consumption of the device to reveal the secret key. In this paper, we propose a design methodology for developing cryptographic circuits using SDMLp Logic Family for DPA Resistant Circuits. A Standard Cell Library is developed for SDMLp cells using SAED90nm PDK. We built the Standard Cell Library from Layout Design to Timing and Power Characterization, and Generation of Milkyway Physical Views. A software DPA attack was performed on AES & DES circuits on SDMLp circuits. Using the proposed design flow, we achieve an area reduction of 35% and power saving of 30% with a delay penalty of 20% compared to an existing DPA-resistant logic family - WDDL.

Synopsys Tools Used:
Custom Designer, Liberty NCX, Milkyway, IC Compiler

Target Audience:
Introductory