|Thursday, September 06, 2012|
10:45 AM - 12:15 PM
|TA1 User & Tutorial Session: Verification - Debug Productivity|
|Simulation-Based Productivity Enhancements Using VCS Save/Restore|
Scot Hildebrandt, Lloyd Cha (Advanced Micro Devices); Vijay Akkaraju, Alok Sinha (Synopsys, Inc.)
Increasing functional complexity of semiconductor designs has resulted in an exponential rise in both directed and constrained random testing. This rise in the regression suites, coupled with shortened project schedules, has exposed the need for non-traditional approaches for productivity improvements in the design engineering phase. Specific bottlenecks that have been identified include multi-day increases in completion of “weekly regressions,” resulting in delay of the resolution of testcase failures. This paper looks at using VCS’s Save/Restore feature to develop steps involving binary image capture of sections of simulation. These “sections” can consist of an aspect common to all tests, like the reset sequence, or allow the skipping of the non-error (passing) portion of a testcase failure. This approach resulted in nearly instantaneous bring-up of test fails for debug and opened the possibility of an overall 10% reduction when applied toward simulation shortcutting in regressions. We conclude the paper by quantifying the benefits and suggesting a roadmap for future projects.
|Using DVE for Exceptional Debug |
Daniel Grabowski (Oracle)
We will present tips and techniques for using DVE to enhance our interactive and post process debug capabilities on our current projects. A focus will be placed on the value of utilizing the interactive debug features present in DVE versus a post-process waveform/log based debug methodology. DVE features that will be highlighted include usage of $tblog/$msglog, UCLI/Tcl, checkpoint/rewind and breakpoints all in conjunction with traditional waveform viewing.
|TA2 User Session: Methodology Solutions with Synopsys Physical Design Tools|
|Staged Physical Verification During Floorplanning to Ensure Predictable LVS Checking|
Frank Malgioglio (IBM); Kevin Brelsford (Synopsys, Inc.)
Shorts and opens, particularly on power and ground, have been a source of last minute frustration in concurrent hierarchical chip designs. Obtaining LVS diagnostics during the floorplanning and fixed-block placement design stages would mitigate these last minute issues but is generally impossible. In this paper, we outline a series of checks in IC Validator designed to evaluate a design prior to detail route and can predict success or failure of full-chip LVS. Results are evaluated on IBM designs in the 32nm and 22nm design nodes.
|Targeting IBM’s 45nm SOI Process with IC Compiler |
Nimit Nguansiri (The MITRE Corporation)
In this paper we discuss our experience with migrating from a traditional bulk CMOS process to IBM’s 45nm Partially Depleted Silicon-On-Insulator (PD-SOI) process. We describe the challenges faced when setting up libraries in Synopsys’s IC Compiler and the importance of bounding multiple interconnect extractions with library characterizations to ensure that all operating conditions are addressed. Also included are suggested techniques for designing with practical timing margin to mitigate On-Chip-Variations (OCV).
|TA3 User & Tutorial Session: Synthesis|
|An End-to-End Approach for Specifying and Verifying False and Multicycle Paths |
Bradley Dobbie, William Stysiack (Cavium, Inc.)
False path and multicycle path timing exceptions represent a significant disconnect between functional simulation and physical implementation. We provide a method to close this disconnect and capture design intent by instantiating special timing constraint buffer modules directly into the RTL source code, verifying them, and synthesizing them into the physical netlist for recognition by the synthesis and timing tools. For functional verification, the buffer modules provide assertion checks to ensure legal behavior under the assumptions of the timing exception. Timing analysis tools search the netlist and recover timing parameters based on the instance name of each buffer module. This method allows designers to confidently use false paths and multicycle paths in their designs and significantly reduces the pre-tapeout timing exception review processes. Making timing exceptions inherent to the design provides a coherent view for functional verification, synthesis, static timing analysis, and clock domain crossing analysis.
|Moving to Design Compiler 2012.06|
Janet Olson (Synopsys, Inc.)
DC Ultra includes comprehensive optimization algorithms to deliver best-in-class quality of results. The Topographical technology in DC Ultra ensures results that correlate to layout, eliminating costly iterations between synthesis and physical implementation. With its advanced feature set and a proven track record of countless design successes, DC Ultra remains to be the synthesis tool of choice. This tutorial will present improvements to the Design Compiler suite with the introduction of the 2012.06 release.
|TA4 User & Tutorial Session: Test|
|Multi-scan Compression Support in an AMD Core|
Thomas Clouqueur, Martin Amodeo (Advanced Micro Devices); Tim Yuan, Lori Schramm (Synopsys, Inc.)
The ability of an IP to support multiple scan compression schemes provides the flexibility of generating compressed patterns with different ATPG tools. This paper describes how AMD added support for DFTMAX compression for an x86 core while continuing support of other scan compression schemes. The architecture was designed to integrate the compression schemes to share as much logic as possible without compromising on the compression performance. This paper describes what type of DFTMAX compression was chosen to best fit the core’s scan architecture, and how the compression gets implemented using AMD’s proprietary VICE  scripts. Problems encountered in this work include LSSD pipestaging unsupported by TetraMAX and general ATPG flow set-up, for which Synopsys provided tool enhancements and support described throughout the paper.
|Test Updates, Yield Improvement and the Influence of Standards|
Adam Cron (Synopsys, Inc.)
This tutorial will provide the latest updates to the Synopsys synthesis-based test solution: DFTMAX Compression and TetraMAX ATPG for comprehensive, high quality manufacturing test, STAR Memory System for memory test and repair, DesignWare IP BIST for high-speed I/O, and Yield Explorer for yield analysis. In addition, standards that allow easier block connectivity in the implementation phase will be discussed along with new developments in the testing of 3D integrated systems.
|TA5 User Session: AMS Verification|
|Analog Mixed-Signal Verification Using UVM|
Warren Anderson, Shyam Sivakumar (Advanced Micro Devices); Vijay Akkaraju, Karim Aoua (Synopsys, Inc.)
This paper describes the application of RTL verification methodology in analog mixed-signal (AMS) designs. The increasing complexity of mixed-signal circuits requires increasd verification to ensure functional correctness. The lengthy run times of SPICE-based mixed-signal simulations are a significant productivity bottleneck in coverage closure and testplan completion. Coupled with limitations of Verilog-only analog models, alternative flows are needed. We consider one such approach: granular representation of low-level analog blocks in Verilog-AMS used to build complete analog circuits that can be instanced in a System Verilog top-level testbench for mixed-signal simulations through VCS and CustomSim. We achieved a decrease of more than an order of magnitude in simulation time and an increase in the number of tests run, enabling faster iden-tification of coverage holes. We expect this flow to form a framework for additional System Ve-rilog concepts in mixed-signal contexts and to increase silicon quality significantly.
|Top-Level Electromigration and IR Drop Analysis of Mixed-Signal Blocks using CustomSim™ Reliability Analysis|
David Fritz, Ari Valero (LSI Corporation); Cheung Lam (Synopsys, Inc.)
The paper describes a process to use CustomSim RA to perform electromigration and IR drop analysis of a large mixed signal block. The CustomSim RA hierarchical approach to circuit si-mulation provides an avenue to analyze current density at a higher level of hierarchy than our standard EM analysis tool. The use of a separate netlist and DSPF file backannotation allow a more time-efficient simulation and DC convergence. The presented flow has been successfully used for electromigration and IR drop analysis on circuits such as: ADC, continuous time filter and analog PLL in a 28nm technology.
|TA6 Tutorial Session: FPGA - Co-Simulating with a Prototype System, Solving P&R Challenges on High-Density FPGAs |
|Simulation, Control and Design Interaction with FPGA-Based Prototyping Systems|
Peter Calabrese (Synopsys, Inc.)
The Universal Multi-Resource Bus (UMRBus) is a high-performance communication bus that can be used for interacting with HAPS Prototyping systems for a variety of applications. These applications include controlling the prototyping systems through setup, register and memory probing, data exchange, debug and simulation interfacing. This tutorial will touch on all aspects of the UMRBus, including co-simulation and SCE-MI, as well a detailed description of the new Synopsys HAPS AMBA transactor library. The transactors give designers the flexibility to partition the SoC design between the SystemC/TLM virtual and FPGA-based prototyping environments at the natural block-level boundaries of the AMBA interconnect. The transactors support a range of AMBA interconnects, including AHB, APB, AXI3, AXI-4 and AXI4-Lite. All these pieces will be tied together to demonstrate a Hybrid-Prototyping solution with HAPS, UMRBus, AMBA Transactors and the virtual prototyping platform- Virtualizer. These applications include controlling the prototyping systems through setup, register and memory probing, data exchange, debug and simulation interfacing. This tutorial will touch on all aspects of the UMRBus, including co-simulation and SCE-MI, as well a detailed description of the new Synopsys HAPS AMBA transactor library. The transactors give designers the flexibility to partition the SoC design between the SystemC/TLM virtual and FPGA-based prototyping environments at the natural block-level boundaries of the AMBA interconnect. The transactors support a range of AMBA interconnects, including AHB, APB, AXI3, AXI-4 and AXI4-Lite. All these pieces will be tied together to demonstrate a Hybrid-Prototyping solution with HAPS, UMRBus, AMBA Transactors and the virtual prototyping platform- Virtualizer.
|Solving P&R Challenges on High-Density Xilinx FPGAs |
Brett Buma (Xilinx)
The ever-increasing need for higher bandwidth has led to designers users larger FPGAs, running at higher clock rates, and needed to achieve high logic utilization. This can sometimes lead to routing challenges and congestion that can impact design closure. To solve these challenges, Xilinx has developed some recommendations to help designers get the most out of their high density FPGA designs. These include logic design, synthesis settings, design analysis and floorplanning.
|Thursday, September 06, 2012|
1:15 PM - 3:15 PM
|TB1 User & Tutorial Session: Verification - UVM|
|Transitioning to UVM from VMM |
Courtney Schmitt (Analog Devices)
This paper discusses the process of transitioning to a UVM design verification environment for current VMM users. Differences and parallels between the two verification methodologies are presented to show that updating to UVM is mostly a matter of learning a new DV syntax. Topics include UVM phases, agents, TLM ports, configuration, sequences, and register models. Best practices and reference resources are highlighted to make the transition from VMM to UVM as painless as possible.
|Implementing Reset Testing with UVM |
Timothy Kramer (The MITRE Corporation)
To meet ever-increasing verification challenges, Accellera has facilitated the development of UVM, which can help improve confidence in a design using constrained random data. UVM provides many features but fails to define a reset methodology, forcing users to develop their own methodology within the UVM framework to test reset. This paper outlines several different reset strategies and enumerates the merits and disadvantages of each. As is the case for all engineering challenges, there are several competing factors to consider, and in this paper the different strategies are compared on flexibility, scalability, code complexity, efficiency, and how easily they can be integrated into existing testbenches. The paper concludes by presenting the reset strategy which proved to be the best compromise of all these factors for our application.
|UVM Past, Present, Future...|
Adiel Khan (Synopsys, Inc.)
As the industry watches UVM mature, discussions about what UVM does and does not contain and why continue to grow.
This presentation will take a look back at what life was like pre-UVM and where we are at with the current UVM implementation. Finally the topic of “what’s next” will be discussed looking at what to expect in the imminent future and near future before we wrap up with speculation as to what UVM might be like in the years to come.
|TB2 Tutorial & Vision Session: Solving Design Challenges at 28nm and Below|
|Designing 100 Billion Transistor Chips|
Brent Gregory (Synopsys, Inc.)
Within the next ten years, we will try designing 100-billion transistor chips. Can Synopsys tools handle so much complexity? 25-year Synopsys veteran EDA programmer, Brent Gregory, thinks they will. He’ll explain why in this light-hearted look at the history of complex inventions. Extrapolating from past trends, he’ll project into the future to show how we can get there.
Are you looking for detailed product roadmaps with specific features and release dates? Then this is *not* the talk for you. Instead, Brent will outline the main factors (such as reuse, hierarchical design, multi-threading, and improved algorithms) driving our ability to handle more complex chips. He will project how these factors will combine to enable the design of incredibly complex chips. Also, he’ll discuss how these changes fit into the larger historical context of the improvement of mankind.
Bring a web-enabled smart phone or laptop to the presentation, and provide your own projections that will be dynamically updated and displayed during the talk.
|Understanding the Source of 28nm and Below Design Challenges (Manufacturing)|
Jonathan White (Synopsys, Inc.)
As process nodes grow smaller, more and more manufacturing challenges have to be taken into account for the timely implementation of physical design. There are many new acronyms, terminology, and buzzwords used to describe new methodologies that need to be accounted for in physical design tools and signoff tools. This session will provide clarity to the new manufacturing challenges, and details into how the designer will live with these challenges in the future.
|Achieving Design Success at 28nm and Below (Physical Design)|
Bill Sieredzki (Synopsys, Inc.)
Advanced technology nodes present a whole new set of design challenges in achieving Timing and Place and Route closure. This tutorial discusses advanced technology design rules (DRC), double pattern technology (DPT), optimal standard cell library layout and demonstrates how IC Compiler will help you achieve design closure. Target audience: Physical designers and managers.
|TB3 User Session: Top-Level Design Closure Using the Galaxy Platform|
|Advanced Design Partitioning with IC Compiler Leveraging Physical Synthesis|
Jack Randall (Advanced Micro Devices)
This paper presents a comprehensive methodology and flow to physically partition a design into several sub-blocks starting from RTL, enable re-running physical synthesis of the sub-blocks, and re-assemble the sub-blocks in IC Compiler for high-quality results. This advanced methodology leverages the capabilities of physical synthesis using Design Compiler Graphical with SPG to explore, optimize, and guide physical partitions prior to IC Compiler’s performance of the splitting. Physical partitioning of a legalized SPG-driven synthesis design generates high-quality automatic pin placements and timing constraints for the resulting sub-blocks. The sub-blocks are further optimized by subsequent physical synthesis from RTL and re-assembled in IC Compiler to perform parasitic extraction and timing analysis re-using the original top-level constraints. Early exploration of the design and initial floorplanning are performed with Design Compiler Explorer. Design Compiler Graphical with SPG is used to drive the design through legalized and optimized placement in IC Compiler before and after partitioning. The described methodology and flow is illustrated with an experimental microprocessor core.
|Effective Top-down Usage from Design Planning to Tapein on 32nm SoC|
Increasing size and complexity of System on a Chip design calls for simplified tools and methods so that engineering effort is spent in solving complex design challenges using small set of tools, simple database management and unified design automation scripting language. This paper highlights such an usage of design planning features to detailed auto-place and route implementation of physical partitions to final chip integration for tapein signoff. The focus of this paper is to describe successful and predictable use of key methods used on a 32nm SoC. Simple feedthru optimization method for a fully abutted design, pseudo hierarchical place-n-route block implementation for timing QOR improvement, novel bump integration using TCL script, full chip speed-path optimization using tool features and SoC clock distribution planning are some of the key techniques presented in this paper.
|A Fast and Flexible Method of Full Chip Clock Planning for 32nm System on a Chip|
Full chip clock planning has been a special topic addressed with implementation styles ranging from full-custom-design to rule-based semi-custom to mix of custom plus automated CTS methods. The need for simplicity and to address late changes has also forced designers to use channel based implementation style for full chip clock distribution. This paper describes clock distribution on a fully abutted 32nm SoC with design planning features in the tool. The focus of this paper is to illustrate key methods developed to get around tool limitations, usage of a nimble database to achieve extremely fast CTS execution, and seamless parallel effort to allow smooth handoff to main floorplanning flow. It highlights clocking challenges and unique logical plus physical components devised to solve clock tree issues and achieve predictable QOR while staying flexible to be able to execute the flow late in the design implementation cycle.
|TB5 Tutorial Session: Custom Signoff|
|Using NanoTime on Complex Clock Designs of Memories and of Custom Digital Macros Part 1: Setup and Analysis of Complex Clocking Schemes in NanoTime Analyzing memories with complex clocking schemes in NanoTime Part 2: Analyzing memories with complex clo |
Norb Heindl (Synopsys, Inc.)
Increasingly complex clocking is now becoming common place in custom designs, especially memory designs, to complete timing closure while maintaining low power and high speeds. Improvements have also been required in modeling in order to better represent basic and complex blocks, like macros and memory blocks, for full-chip static timing sign-off with PrimeTime. This tutorial will detail some of these new features that have been added into NanoTime to improve clocking analysis and modeling. This tutorial will also introduce the latest functionality in NanoTime for the design and characterization of memories. All custom circuit designs and memory designers should attend this session.
|TB6 Tutorial Session: FPGA - Synopsys Design Constraints in FPGA Space, High Reliability Techniques in Premier|
|Using Synopsys Design Constraints (SDC) for FPGA |
Gene Stuckey (Synopsys, Inc.)
As FPGA designs are growing in size and complexity, it has necessary to define accurate design constraints for synthesis in order to guarantee correct behavior of FPGA designs similar to what has been done for many years in ASIC designs. With this purpose, all FPGA implementation tools are moving to the standard Synopsys Design Constraint format which guarantees the same interpretation of the design constraint throughout the design process. This leads to increasing design predictability. In this session you will learn how Synplify Pro and Synplify Premier handle Synopsys Design Constraints.
|High-Reliability Design Techniques in Synplify Premier |
Carl Cleaver, Meera Srinivasan (Synopsys, Inc.)
High reliability (high rel) design techniques, once considered primarily for FPGA's operating in space, are becoming critical for Earth based FPGA's due to shrinking circuit feature sizes. High rel techniques can consist of methodology, tool features, device features and design practices. This tutorial will examine topics such as TMR (Triple Mode Redundancy), ECC (Error Correction Code), power consumption, and timing analysis. Examples of how to verify the techniques and their resource cost will be examined.
|Thursday, September 06, 2012|
3:30 PM - 5:00 PM
|TC1 User & Tutorial Session: Verification - Complex Designs|
|Assert Your Independence! Adopting the OVL Assertion Library as an IP/SoC Standard|
John A. Thomson (Advanced Micro Devices)
Assertion-based verification is a powerful technique that aids debug in semiconductor verification by providing locality and visibility of failures. Unfortunately, semantic and simulator-specific differences between assertion languages such as SVA, PSL, and OVA can cause significant problems when re-using design and verification IP in an IP/SOC model. Assertions written in one language may not operate correctly when enabled concurrently with another. The languages do not share the same control and messaging frameworks, leading to false failures, missed assertions, and the potential for bug escapes. Problems also occur when using properties in non-simulation environments such as hardware emulation, LEC, and formal verification tools. To counter these problems, this paper describes a standard methodology that uses the Accellera OVL Assertion Library. This paper describes our migration to the OVL standard and key problems encountered in deployment, and describes potential enhancements to our methodology relative to IEEE 1800-2009.
|Discovery Verification IP for Advanced Protocol Checking and Debug|
Tushar Mattu (Synopsys, Inc.)
Over the last couple of years protocols like AMBA’s AXI4 and ACE, USB3.0, HDMI among others have made verifying SoC designs much most complicated. This complexity has increased the time to verify, requiring sophisticated system level monitors and checkers to help improve debug times. Traditionally, building verification IPs (VIP) was left to home grown solutions or third party solutions using outdated technologies. In this tutorial you will learn how the latest generation of VIP from Synopsys accelerates and simplifies the adoption of these complexity technologies through the use of system level monitors and protocol aware debugging tools.
|TC2 Tutorial Session: Physical Design - IC Compiler 2012.06 Update and Top-Level Design Closure|
|Migrating to IC Compiler 2012.06: Release Update |
Dave Power (Synopsys, Inc.)
IC Compiler’s latest release focuses on helping IC designers achieve higher frequencies more efficiently. The 2012.06 release delivers faster design closure with new top-level optimization capabilities, dataflow analysis, expanded support for highly fragmented floorplans, and multisource clock tree synthesis that provides better variation tolerance. There are also new technologies that address advanced process effects and improved in-design features. Learn about these advancements in IC Compiler and how you can use them to achieve higher frequencies in your design.
Target audience: This is an informative session for all Physical designers and managers.
|Faster Top-Level Closure With Transparent Interface Optimization (TIO)|
Brad Ragazzo (Synopsys, Inc.)
Transparent Interface Optimization (TIO) in IC Compiler is a new capability that addresses the challenges of gigascale design and enables faster top-level closure. This tutorial will provide designers technical information on TIO, its usage, current capabilities and roadmap.
Target audience: Design and CAD engineers and managers responsible for physical implementation and verification.
|TC3 User Session: Physical Design - Advanced Clock Techniques in IC Compiler|
|Design and Analysis of a Conditional Clock Mesh |
Ranjith Hallur, Bill Stysiack (Cavium, Inc.)
In High-Speed Designs, minimizing clock skew and achieving low power is one of the biggest challenge. Traditional Clock Tree Synthesis (CTS) can deliver a low area and low power clock distribution network, but is not tolerant to variation. On the other hand, Clock grids provide low skews at the cost of area and power.
In this paper, we propose a solution using ICC’s Clock Mesh technology, to design and analyze conditional clock meshes for high-speed designs. In the conventional clock mesh flow, a clock mesh drives the clock gaters and the mesh itself is unconditional. In our proposed approach, we push the clock gaters back one level. A coarser mesh drives these clock gaters and the denser mesh is driven by these clock gaters, thereby making the denser mesh conditional and saving power.
This approach provides Low Skew and Lower Power clock distribution.
|Clocks Against Variation|
Gerard M. Blair (LSI Corporation)
Cells vary, wires vary; skew is very costly. By considering how the timing of a clock tree’s com-ponents changes under process variation, we identify how to make branches relatively invariant and illustrate with a simple implantation strategy and example.
|TC4 Tutorial Session: PrimeTime and Constraints|
|Primetime/Primetime-SI 2011/2012 Special Topics and Methodology|
Robert Grozier (Synopsys, Inc.)
Over the last 2 years Primetime has continued to improve usability, performance, and capacity. Presentation will review selection of changes you might have missed for methodologies and features; report_timing, muli-core, crosstalk analysis, etc.
|Minimizing Risk in Multi-clock Designs with Galaxy Constraint Analyzer|
Mark DiGiovanni (Synopsys, Inc.)
Today’s multi-clock designs make constraint development more difficult, and increase the risk of clock setup errors impacting your schedule. In this tutorial we will show how Galaxy Constraint Analyzer (GCA) can be used to confirm you have complete and correct constraints, and to identify structural problems in your design that impact the integrity of your clock network. During the tutorial we will explore the host of debug options available in GCA that allow you to better understand the issues identified and guide you to solutions. We’ll also look at how GCA interfaces with DC Explorer to enable constraint analysis at the earliest stages of your design flow.
|TC5 Tutorial & User Session: AMS Formal Verification|
|ESP Memory Redundancy Verification|
Dave Hedges (Synopsys, Inc.)
ESP-CV uses symbolic simulation to verify Verilog and SPICE designs, usually in an equivalence checking context. This tutorial gives a quick introduction to ESP-CV and how recent redundancy verification features are used to verify various types of redundancy circuitry used in full-custom or compiler memory blocks. These capabilities go beyond equivalence checking to true circuit behavioral verification. Target audience: Full-custom or compiler memory block designers.
|Exhaustive Equivalence Checking on ROM Macros|
Keerthi Chamakura (University of Texas at Dallas); Lindsey Tessier, Baosheng Wang (Advanced Micro Devices)
Read-only memory (ROM) is a key component in microprocessors, and exhaustively verifying its implementation against RTL in terms of structure and content is crucial. Traditional static-based logic equivalence checking methods fail to cover dynamic structures, usually used to build ROMs in high-performance microprocessors. More advanced equivalence checking methodologies are required to provide 100% verification coverage while maintaining a reasonable run-time.
In this paper, we present an exhaustive equivalence checking framework to validate ROMs through external tools (e.g., Formality, ESP-CV) and homegrown scripts. We first obtained basic verification coverage by applying the traditional equivalence checking method and tooling (e.g., Formality) on ROM RTL and gates abstracted from SPICE with an internal tool. We secondly applied ESP-CV on ROM RTL and SPICE directly to cover the missing dynamic structures in a reasonable run-time. Thirdly, a home-grown script was developed to ensure that ESP-CV did not report any coverage loss on ROM dynamic structures. Lastly, with the same internal script, the ROM contents were fully verified by comparing the intended contents with the ESP-CV coverage report.
Based on our experiments, compared with traditional static-based equivalence checking techniques, the proposed technique is proven fast and exhaustive.
|TC6 Tutorial Session: Flow Automation and Programmable Design - Lynx & Processor Designer|
|Managing Power on Hierarchical Designs using UPF with Lynx Design System / Designing High-Performance ASICs with Lynx Design System|
Cyrille Thomas, Kristine Westland (Bull SAS) (Synopsys, Inc.)
Bull SAS as a key player in HPC will share its experience using Lynx Design System for the most advanced chipsets using 40 and 28nm technologies in a multi-site and multi-project environment. In this presentation we will discuss motivation, actual experience and benefits using pre-validated flows, advanced visualization, and supervision tools for concurrent project design including process migration, flow migration and specific project sub-flow customization. The session will conclude with a tutorial presented by Synopsys on how to achieve faster timing closure on hierarchical designs utilizing the Lynx Design System.
|Designing Programmable Hardware Accelerators: Gaining Flexibility Without Compromising Power, Area and Performance|
Drew Taussig (Synopsys, Inc.)
Dealing with change has become more important than ever—whether you need to support a new emerging standard or respond to new functionality that your competition just released. So what about trading fixed hardware implementations for a programmable hardware accelerator? Is it possible to design such a programmable hardware that is flexible enough to deal with multiple standards and different use cases, while meeting power, performance and area constraints?
In this session we will cover how Synopsys Processor Designer allows hardware designers to efficiently design and verify programmable hardware, covering the creation of optimized RTL code, software tools such as assembler, linker, compiler and instruction-set simulator as well as a SystemC model from a single formal input specification.
|User Experience Verifying Ethernet IP Core|
Puneet Rattia (Altera)