|DAC 2016 Samsung/Synopsys Breakfast: Ready to Design at 10nm!|
Samsung and Synopsys are enabling design teams to create advanced designs for high performance computing and mobile applications on 10nm FinFET technology. On June 7, 2016, Synopsys hosted a Samsung 10nm FinFET breakfast event at DAC. At this event, attendees heard how “Relentless Collaboration” is extending to 10nm FinFET design enablement best practices and saw highlights of the 10LPE Foundry Reference Flow and ARM® Cortex®- A53 CPU, 10LPE Reference Implementation proof point.
Kelvin Low, Samsung Semiconductor; Phil Dworsky, Synopsys; JC Lin, Synopsys; Andy Potemski, Synopsys
|DAC 2016 Custom Compiler Lunch Videolog: Cutting Layout Tasks from Days to Hours|
FinFET devices have added significant complexity to the design flow, and many companies are seeking new solutions for custom design. Custom Compiler’s pioneering visually-assisted automation can cut layout tasks from days to hours.
On June 7, 2016, Synopsys hosted a Custom Compiler Luncheon at DAC. At this event, attendees heard users discuss their experiences with custom design challenges and how they have deployed Custom Compiler to improve their custom design productivity for both FinFET and established nodes.
GSI, Samsung, STMicroelectronics, Synopsys IP
|DAC 2016 Circuit Simulation Lunch Videolog: Robust AMS Design Verification at Advanced Nodes|
On June 6, 2016, Synopsys hosted a Circuit Simulation Luncheon at DAC. At this event, attendees heard Industry leaders from Oracle, Samsung and STMicroelectronics discuss their design verification challenges that stem from cutting-edge advanced technologies and increasing design complexity in memory, analog, and mixed-signal applications, and how they overcome such challenges by using Synopsys AMS circuit simulation solutions to ensure design robustness.
Sam Lo, Hardware Development Manager, Oracle; Zach Coombes, CAD Engineer, Samsung; Atul Bhargava, Sr. Staff Engineer, STMicroelectronics
|Samsung and Synopsys|
Kelvin Low highlights Samsung and Synopsys' collaboration on 14nm design enablement, IP and the use of the Lynx Design System
|Enabling Network Computing Design with 14nm LPP FinFET Technology|
On June 9, 2015, Synopsys, Samsung and ARM co-hosted a breakfast at the Design Automation Conference. At this event, attendees learned how Samsung, ARM and Synopsys are utilizing Samsung’s 14nm LPP technology to meet the added functionality needs of network computing ARM-based designs.
Kelvin Low, Samsung; Wolfgang Helfricht, ARM; Andy Potemski, Synopsys; Phil Dworsky, Synopsys (moderator)
|DAC 2015 - Custom Design Luncheon|
On June 9, 2015, Synopsys hosted a Custom Design Luncheon at DAC. At this event, attendees heard industry leaders from Socionext, Samsung, and Synopsys’ IP Group share their experiences meeting the challenges of FinFET custom design, and discuss how they have deployed Synopsys’ custom design tools to improve their custom design productivity.
|A Simple Formula for Success with Next-Generation Wearables to High-Performance |
Through relentless collaboration efforts in all aspects of the design cycle, key ecosystem partners - Samsung Foundry, Synopsys and ARM - have made it easier for leading customers to achieve first-time-silicon success with their leading-edge 28nm and 14nm SoC designs. With this continued commitment to reducing risk and minimizing the design cycles, these three companies are bringing differentiated solutions to customers, including silicon-proven PDKs, foundation IPs, advanced IPs and design flows.
Rob Aitken, ARM; Glenn Dukes, Synopsys; Kelvin Low, Samsung SSI; Phil Dworsky, Synopsys
|Customer Insight Sessions: High Performance, Gigahertz+ Design Success with the Galaxy Implementation Platform|
At DAC 2012, Industry experts from Samsung Electronics and NVIDIA discussed the latest high performance design trends, challenges and solutions. You will learn about innovations in high-performance technology that help address your gigascale, gigahertz+ and advanced geometry design challenges.
In this video, Jun Seomun from Samsung discusses high performance mobile SoC design challenges & solutions.
Jun Seomun, Samsung
|PrimeTime SIG DAC 2012|
The Synopsys PrimeTime SIG is an active community for all PrimeTime users and design engineers who want to stay connected with the latest developments in the field of Static Timing Analysis (STA).
At the PrimeTime SIG 2012, Byung-Su Kim, Senior Engineer, Design Technology Team, System LSI, Samsung Electronics discussed the benefits of HyperScale technology.
Byung-Su Kim, Senior Engineer, Design Technology Team, System LSI, Samsung Electronics