Webinars 

Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow - Simplified Chinese
Simplified Chinese: Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Chung Yang, CAE, Synopsys
May 28, 2014

Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow - Traditional Chinese
Traditional Chinese: Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Chung Yang, CAE, Synopsys
May 28, 2014

Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow
Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Carol Scemanenco, Senior Staff Engineer, Synopsys
May 27, 2014

TSMC and Synopsys at 16nm: Collaborating to Create Comprehensive Solutions for Optimal FinFET Design
TSMC and Synopsys describe their broad, co-developed solutions for 16-nm design that are architected to bring the fastest node enablement to their mutual customers
Chiming Li, Technical Manager Design Methodology & Service Marketing Program, TSMC; Dr. Henry Sheng, Senior Director of R&D, Synopsys
Nov 05, 2013

TSMC and Synopsys at 16nm: Collaborating to Create Comprehensive Solutions for Optimal FinFET Design
TSMC and Synopsys describe their broad, co-developed solutions for 16-nm design that are architected to bring the fastest node enablement to their mutual customers.
Chiming Li, Technical Manager Design Methodology & Service Marketing Program, TSMC; Dr. Henry Sheng, Senior Director of R&D, Synopsys
Nov 05, 2013

TSMC & Synopsys Present: DFTMAX Compression, IEEE 1500-based Hierarchical Test & iJAG
As the complexity of systems-on-chip increases, so does the need to leverage standards-based methodologies to implement test in a hierarchical manner, across multiple cores.
Dr. Saman Adham, Senior Manager, TSMC; Robert Ruiz, Product Marketing Manager, Synopsys; Adam Cron, Principal Engineer, Synopsys
May 23, 2013

Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Anderson Chiu, Technical Manager, TSMC; Beifang Qiu, Senior R&D Manager, Synopsys
Dec 05, 2012

Double Patterning Ready Extraction and Signoff: TSMC - Simplified Mandarin
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Anderson Chiu, Techincal Manager, TSMC; Beifang Qiu, Senior R&D Manager, Synopsys
Dec 05, 2012

Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update - Traditional Mandarin
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Beifang Qiu, Technical Manager, Synopsys; Anderson Chiu, Senior R&D Manager, TSMC
Dec 05, 2012