TSMC - Synopsys Collaboration News 



Oct 08, 2014TSMC Selects Synopsys as "2014 Partner of the Year" for Interface IP and Joint Development of 16-nanometer FinFET Plus Design Infrastructure


Sep 30, 2014TSMC and Synopsys Accelerate Custom Design Productivity for 16FF+ Process
Collaboration Enables Best Practices for Custom Implementation Productivity with FinFET Devices

Sep 25, 2014Synopsys Tools Achieve TSMC Certification for 16-nm FinFET+ Process and Both Companies Enter 10-nm FinFET Collaboration
Certification of Digital and Custom Tools Enables Early Adopters to Realize QoR Benefits of the New Processes

May 27, 2014Synopsys and TSMC Collaborate to Validate DesignWare IP in TSMC 16-nm FinFET Process
Silicon Success of DesignWare USB 3.0 femtoPHY, Logic Libraries and Embedded Memories in TSMC 16-nm FinFET Process Verifies Robustness of Both IP and Process

Apr 14, 2014TSMC Certifies Synopsys Digital and Custom Solution for V1.0 N16 Process
Certification Enables Designers to Realize the Power, Performance and Area Benefits of FinFET Technology

Oct 14, 2013Synopsys and TSMC Collaborate to Deliver 16-nm Custom Design Reference Flow
TSMC Certifies Analog/Mixed-Signal Products for 16-nm Design Requirements

Oct 01, 2013Synopsys Selected as TSMC’s 2013 “Interface IP Partner of the Year” for Fourth Consecutive Year
Award Recognizes Technical Leadership, Number of Customer Tape-Outs, and Outstanding Customer Support

Sep 23, 2013Synopsys Implementation Solution Included in TSMC 16-nm Reference Flow for FinFET Design


Sep 19, 2013Synopsys Announces Immediate Availability of Broad Portfolio of Interface IP for TSMC's 20SoC Process


Sep 08, 2013TSMC and Synopsys Extend Custom Design Collaboration into 16-nm
TSMC Certifies Laker Custom Design Solution for 16-nm FinFET and Provides iPDK

May 29, 2013TSMC Certifies Synopsys' Digital and Custom Solutions for 16-nm FinFET Process
V0.1 Certification Based on Collaboration over Key Foundational Technologies

Nov 14, 2012Synopsys and TSMC Enable Lithography Compliance Checking for 20nm
Collaboration brings key Synopsys technology to TSMC DFM Data Kit

Oct 17, 2012Synopsys Wins TSMC's 2012 "Interface IP Partner of the Year" Award
Excellent Customer Support, Technical Leadership and Number of Customer Tape-Outs Cited as Key Selection Criteria

Oct 17, 2012TSMC Awards Synopsys "Partner of the Year 2012" for 20nm Reference Flow
The award recognizes Synopsys' broad and deep technical expertise and shared commitment to the development and delivery of TSMC’s 20nm reference flow

Oct 15, 2012Synopsys and TSMC Collaborate for 20nm Reference Flow
Design Tools in Synopsys® Galaxy™ Implementation Platform selected in 20nm Reference Flow for Physical Implementation, RC Extraction, Timing Analysis and Physical Verification

Oct 11, 2012Synopsys and TSMC Deliver 3D-IC Design Support
Design Tools Selected in TSMC's First Integrated, Validated Reference Flow and Design Kit Enabling Multi-Die Integration Using TSMC CoWoS Technology

May 31, 2012Synopsys Design Implementation Tools Receive TSMC 20nm Phase I Certification


Mar 28, 2012Synopsys, Altera and TSMC Collaborate to Deliver Silicon-Accurate Parasitic Modeling and Extraction for 28-nm Processes
Altera Deploys Synopsys' StarRC Extraction Solution to Accelerate Time to Market for 28-nm FPGA Designs

Feb 14, 2012Synopsys Announces DesignWare Embedded Memories and Logic Libraries for TSMC 28-nanometer Processes
Advanced Memory and Logic IP Enable Designers to Optimize 28-nm SoCs for Both Maximum Performance and Low Power Consumption

Nov 07, 2011Synopsys Awarded TSMC's Interface IP Partner of the Year
Technology Leadership and Outstanding Customer Support Cited as Key Selection Criteria

Jun 02, 2011Synopsys and TSMC Collaborate to Deliver Custom Design Solution for 28nm Analog/Mixed-Signal Reference Flow 2.0
Synopsys Galaxy Custom Designer Provides New Capabilities to Address Advanced Process Node Design Challenges

May 26, 2011Synopsys Delivers 28-nm Design Solutions and Advanced System-Level Capabilities for TSMC Reference Flow 12.0
Flow provides optimized methodologies to shorten time-to-market and time-to-volume for designers using TSMC's 28-nanometer process technology

Nov 17, 2010Synopsys' IC Validator Completes Qualification for TSMC's 40-nm and 65-nm iDRC/iLVS Physical Verification
Runset Availability Enables Faster Tapeouts with In-Design Physical Verification

Oct 21, 2010Synopsys Awarded TSMC's 'Interface IP Partner of the Year'
Delivers a Broad Portfolio of High-Quality, Silicon-Proven IP for TSMC Processes