| Jan 22, 2013 | Synopsys Accelerates Adoption of FinFET Technology with Production-Proven Design Tools and IP
FinFET Technology Support Developed over Five-year Collaboration with Industry Leaders
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| May 31, 2012 | GLOBALFOUNDRIES Silicon Validates 28nm AMS Production Design; Reveals Digital and AMS Support for Double Patterning at 20nm
Extensions and validation of analog/mixed-signal flow at 28nm; Advanced support for 20nm passes initial qualification milestones
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| May 30, 2012 | Synopsys’ Collaboration with Industry Consortium Yields Double Patterning Technology Models for Parasitic Extraction
Unique Fabless-Foundry Sharing Model Allows Automated Volume Diagnostics to Identify and Prioritize Systematic Failure Mechanisms
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| May 30, 2012 | GLOBALFOUNDRIES Selects Synopsys' Yield Explorer for Faster Yield Ramp
Unique Fabless-Foundry Sharing Model Allows Automated Volume Diagnostics to Identify and Prioritize Systematic Failure Mechanisms
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| Dec 14, 2011 | Synopsys Enables Silicon Success for GLOBALFOUNDRIES’ First Complex 20-nm Design
GLOBALFOUNDRIES Tapeout Reinforces Synopsys IC Compiler as the Leading Choice for 20 Nanometers
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| Dec 08, 2011 | Synopsys’ IC Validator Certified by GLOBALFOUNDRIES for 28-nm, 40-nm and 65-nm Design
Runset Availability Brings Benefits of In-Design Physical Verification to Mutual Customers
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| Jul 11, 2011 | Synopsys and GLOBALFOUNDRIES Collaborate to Deliver Interoperable Process Design Kits (iPDKs)
Synopsys Custom Design Solution Now Supported by GLOBALFOUNDRIES 65nm Process Technologies
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| Feb 01, 2011 | Synopsys Collaborates with Industry Consortium on Solutions to Model Latest 28-nm Parasitic Effects
IMTAB Group in IEEE-ISTO Ratifies Interconnect Technology Format Extensions
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| Jan 17, 2011 | Synopsys Announces Production-Ready Lync Design System Optimized for Common Platform 28-nm High-K Metal Gate Technology
Collaboration Brings Integrated and Validated IP, Design Tools and Methodology to Facilitate Low Power, High-performance Mobile System-on-Chip Design
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| Jan 13, 2011 | GLOBALFOUNDRIES Unveils Industry’s First 28nm Signoff-Ready Digital Design Flows
Multiple 28nm design flows available through collaboration with leaders in EDA/IP ecosystem
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| Aug 04, 2010 | GLOBALFOUNDRIES to Develop DesignWare Interface PHY IP for 28-Nanometer Technologies
Collaboration Enables Faster Time-to-Volume for Advanced High-Performance SoC Designs
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| Jun 14, 2010 | ARM, IBM, Samsung, GLOBALFOUNDRIES and Synopsys Announce Delivery of 32/28nm HKMG Vertically Optimized Design Platform
Companies demonstrate strength of collaboration at 47th DAC
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| Jun 14, 2010 | Synopsys Delivers Optimized Lynx Design System for Common Platform 32/28-nm Technology
Integrated and Pre-Validated Solution Speeds Design of Advanced SoCs
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