Common Platform 

Access Innovation…Today and Tomorrow

32/28nm Enablement Delivered
Synopsys, the Common Platform (IBM, Samsung and GLOBALFOUNDRIES) and ARM have delivered the industry’s first complete vertically optimized design platform for 32/28nm development. Several years of collaboration between the companies led to this new advancement in SoC design.

The RTL-to-GDSII implementation solution reduces risk and total design costs for optimized 32/28nm HKMG ARM Cortex processor-based SoC designs. The platform includes:

  • ARM® Cortex™ high-performance, low-power processor architecture and optimized suite of physical IP including standard cells, power management kit, memory compilers and interface IP, for the 32/28nm HKMG process
  • Synopsys Lynx Design System, enabled by the Galaxy™ Implementation Platform with IC Validator In-Design physical verification, and the Synopsys DesignWare® portfolio of interface IP.
  • 10 test chips produced through the three-way collaboration in 32 and 28nm HKMG process technology. Producing these chips has helped validated the design platform, including Common Platform PDKs, ARM Artisan Physical IP and Cortex processors, Synopsys Interface IP, core tool enablement and design methodology for accelerating silicon success.
  • Collaborating to synchronize semiconductor manufacturing facilities for the manufacture 28nm low-power HKMG semiconductors for a new generation of mobile devices, providing the flexibility of multi-sourcing based on the planned synchronization of fabs by members of the Common Platform alliance (IBM, Samsung and GLOBALFOUNDRIES).

Videos about our collaboration

Overview Video - Why Collaborate?

Watch the 32nm Collaboration Video – Innovation Optimized!
ARM, Common Platform and Synopsys executives share their views on the recent collaboration announcement:

Dr. Aart de Geus, Chairman of the Board and CEO, Synopsys
Michael Cadigan, General Manager, Microelectronics Division, IBM Systems and Technology Group
Dr. C.S. Choi, Executive Vice President, LSI Division, Samsung Electronics
Warren East, CEO, ARM Holdings

The Common Platform Partnership
IBM, Samsung and GLOBALFOUNDRIES have joined together to establish a new flexible semiconductor foundry model known as the Common Platform partnership. Combining expertise from
each company, they have jointly developed a family of leading-edge CMOS process technologies and advanced manufacturing capabilities. By sharing a common set of design rules and manufacturing processes, designs are created once and can be manufactured at any single foundry or at any combination of them. The Common Platform Overview provides more details about this new approach to the foundry market.

Synopsys has collaborated with each of the Common Platform companies for many years. When the Common Platform partnership was formed it was only natural that they extend their successful Synopsys relationships to the new effort.

Collaboration Benefits
You benefit from the collaboration between IBM, Samsung, GLOBALFOUNDRIES and Synopsys in several ways:

  • Reference Flows
    Synopsys has worked with the Common Platform companies and ARM's Artisan Physical IP Division to develop, test, and deliver complete reference flows that allow you to transform your RTL into foundry-ready GDSII.
    • Please see the Common Platform Reference Flow page for more details.
    • The 28nm and 32nm reference flows based on the Galaxy Implementation Platform and validated using ARM Artisan Physyical IP, takes full advantage of the latest Galaxy enhancements. This includes Design Compiler Graphical physical guidance to IC Compiler that tightens timing and area correlation for a faster, predictable and convergent path from RTL to GDSII; ZRoute DFM-optimized routing; In-Design DRC auto fixing with IC Validator, dynamic rail analysis with PrimeRail, and final stage leakage reduction that preserves timing. For more detail, please see the 32nm Reference Flow and 28nm Reference Flowannouncements.
    • The 45nm low power reference flow offers a comprehensive design flow built around Synopsys' Eclypse™ Low Power Solution and the widely adopted Unified Power Format (UPF) language, using the latest technology files from the Common Platform™ foundries and ARM® Artisan Physical IP standard cells, I/Os, memories and the Power Management Kit for the CMOS11LP process. For more detail, please see:
      45nm Reference Flow Announcement
    • The 65nm reference flow adds 65nm capabilities to the design flow, including improving manufacturability using the critical area reduction capabilities of IC Compiler™ using foundry-supply defect data. A variety of new 65nm specific design rules are incorporated into place and route and physical verification (DRC) tools. For more details, please see the
      65nm Reference Flow Announcement
    • The 90nm reference flow is a complete RTL-to-GDSII design flow focused on quickly reaching design closure by simultaneously addressing power, timing, area, and signal integrity challenges. For more details, please see:
      90nm Reference Flow Announcement

    The reference flows were created by Synopsys Professional Services and independently validated by the Common Platform partners.

    The 28nm, 32nm, 45nm, 65nm and 90nm reference flows are available at no charge to Common Platform customers and can be requested using an on-line form in SolvNet.

  • Interface IP
    The complexity of today’s SoC design coupled with accelerated time-to-market and reduced integration risk pressure, necessitates use of high quality synthesizable implementation and verification SoC infrastructure IP and silicon-proven Interface IP. In addition to a comprehensive library of DesignWare synthesizable implementation and Verification IP, Synopsys also offers a broad portfolio of silicon-proven interface IP solutions optimized for the 28nm, 32nm, 45nm, 65nm, and 90nm Common Platform process technologies including USB, DDR, HDMI, PCI Express, SATA, and XAUI.
  • Design Services
    Synopsys Professional Services combines application-specific design experience with in-depth knowledge of the Common Platform reference flow and silicon IP to assist your team in implementing your design in a Common Platform technology.