| Feb 05, 2013 | GLOBALFOUNDRIES and Synopsys To Provide Design Environment for 14 nm-XM FinFET
IP and design tool flows accelerate implementation of robust non-planar architecture for mobile products
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| Jan 22, 2013 | Synopsys Accelerates Adoption of FinFET Technology with Production-Proven Design Tools and IP
FinFET Technology Support Developed over Five-year Collaboration with Industry Leaders
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| Dec 20, 2012 | Samsung and Synopsys Achieve First 14-nanometer FinFET Tapeout
Collaboration Encompasses Synopsys IP, Design Implementation, Extraction and Signoff Tools
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| May 31, 2012 | GLOBALFOUNDRIES Silicon Validates 28nm AMS Production Design; Reveals Digital and AMS Support for Double Patterning at 20nm
Extensions and validation of analog/mixed-signal flow at 28nm; Advanced support for 20nm passes initial qualification milestones
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| May 30, 2012 | Synopsys’ Collaboration with Industry Consortium Yields Double Patterning Technology Models for Parasitic Extraction
Unique Fabless-Foundry Sharing Model Allows Automated Volume Diagnostics to Identify and Prioritize Systematic Failure Mechanisms
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| May 30, 2012 | GLOBALFOUNDRIES Selects Synopsys' Yield Explorer for Faster Yield Ramp
Unique Fabless-Foundry Sharing Model Allows Automated Volume Diagnostics to Identify and Prioritize Systematic Failure Mechanisms
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| Dec 14, 2011 | Synopsys Enables Silicon Success for GLOBALFOUNDRIES’ First Complex 20-nm Design
GLOBALFOUNDRIES Tapeout Reinforces Synopsys IC Compiler as the Leading Choice for 20 Nanometers
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| Dec 08, 2011 | Synopsys’ IC Validator Certified by GLOBALFOUNDRIES for 28-nm, 40-nm and 65-nm Design
Runset Availability Brings Benefits of In-Design Physical Verification to Mutual Customers
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| Jul 11, 2011 | Synopsys Announces Critical Milestone in 20-nm Design Enablement Collaboration With Samsung Electronics
Samsung Successfully Tapes Out First 20-nm Test Chip Using IC Compiler and In-Design Physical Verification with IC Validator
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| Jan 17, 2011 | Synopsys Announces Production-Ready Lync Design System Optimized for Common Platform 28-nm High-K Metal Gate Technology
Collaboration Brings Integrated and Validated IP, Design Tools and Methodology to Facilitate Low Power, High-performance Mobile System-on-Chip Design
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| Aug 04, 2010 | Synopsys and GLOBALFOUNDRIES to Develop DesignWare Interface PHY IP for 28-nanometer Technologies
Collaboration Enables Faster Time-to-Volume for Advanced High-Performance SoC Designs
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| Jun 14, 2010 | ARM, IBM, Samsung, GLOBALFOUNDRIES and Synopsys Announce Delivery of 32/28nm HKMG Vertically Optimized Design Platform
Companies demonstrate strength of collaboration at 47th DAC
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| Jun 14, 2010 | Synopsys Delivers Optimized Lynx Design System for Common Platform 32/28-nm Technology
Integrated and Pre-Validated Solution Speeds Design of Advanced SoCs
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| Jun 10, 2010 | Samsung Electronics Achieves First-Pass 32nm Silicon Success Using Synopsys Galaxy Implementation Platform
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| Sep 30, 2009 | Common Platform Alliance Qualifies Synopsys IC Validator for 32-nm Design Rule Checking
In-Design Physical Verification Pivotal in Reducing Time to Tapeout for Advanced Designs
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| Jul 27, 2009 | 32nm Collaboration - Common Platform ARM and Synopsys Vertically Optimized Solution
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| Jul 27, 2009 | ARM, Chartered, IBM, Samsung, and Synopsys Collaborate to Deliver Vertically Optimized Solution for 32/28nm Mobile SoC Designs
Companies combine low-power processor architecture, integrated design flow, and system-level IP on Common Platform foundry process
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| Jun 23, 2009 | Synopsys and TSMC Deliver Accurate Lithography Verification for 28nm Designs
Encapsulated Access to Foundry Data and Tool Chain Accelerates Time to Market and Improves Yields
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| Jun 09, 2009 | TSMC Selects Synopsys Galaxy Implementation Platform for Integrated Sign-off Flow
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| Jun 09, 2008 | Synopsys Delivers 45-Nanometer Low Power Reference Flow for Common Platform Technology Validated with ARM Physical IP
Comprehensive Flow Enhanced with Integration of Eclypse Low Power Solution Enabled by Unified Power Format
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| May 24, 2007 | Synopsys Achieves Two IP Firsts: 65-nm PCIe and 90-nm USB Compliance Utilizing Common Platform Technologies
Single GDSII, Multi-Foundry Connectivity IP Enables Designs Using Common Platform Processes
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| Apr 05, 2007 | Synopsys' Reference Flow for Common Platform Technology Wins Prestigious IBM Beacon Award
Complete 65-Nanometer Design Flow Recognized as Common Platform Technology Critical Success Factor
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| Jul 19, 2006 | Synopsys Delivers First 65-nm Reference Flow for IBM, Samsung and Chartered
Common Platform Technology Reference Flow Adds Critical Area Design-for-Manufacturing Capability in IC Compiler
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| Jul 11, 2006 | IBM and Chartered Team With Synopsys for Mixed-Signal Connectivity IP at 65 nm
Synopsys USB, PCIe, SATA and XAUI PHYs for High-Volume, Low-Power Applications Available for Foundries' Leading-edge Processes
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