Vertically Optimized 32/28nm Solution for Mobile SoC Design
Wednesday, Oct 21
8:30-9:00am - Registration and Continental Breakfast
9:00-10:30am - Program
Santa Clara Convention Center Ballroom H

This special 3-way go-deep session hosted by ARM, the Common Platform™ (IBM, Chartered Semiconductor Manufacturing and Samsung Electronics) alliance, and Synopsys introduces a new level of collaboration necessary to address the cost and technical challenges associated with advanced mobile SoC design and manufacturing. As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential.

Learn how this extended collaboration enables customers to deliver optimized ARM®-based 32/28LP mobile SoC designs whilst achieving faster time-to-market at reduce risks and design costs. We explain how this collaboration is enabling a proven turnkey design solution for optimizing innovation and accelerating your design with best-in-class technology, physical and processor IP and tool/flow solutions for the Common Platform's 32nm/28nm high-k metal-gate (HKMG) process technology.

Innovation and collaborations highlights include:

• HKMG Process Technology Enablement:
  32/28-nanometer (nm) low-power/low-leakage, high-k metal-gate (HKMG) material science breakthroughs and synchronized foundry services through the Common Platform alliance

  Dr. Jaga Jagannathan, Director, 32/28 Technology Productization, IBM Semiconductor R&D Center

• Foundation, Enhanced and Processor IP Enablement:
  ARM high-performance, low-power processor architecture for mobile applications, and optimized suite of physical intellectual property (Physical IP) on Common Platform 32/28LP foundry process

  Dr. Dipesh Patel, Vice President of Engineering at ARM's Physical IP Division

• Tool, Connectivity IP and Flow Enablement
  Synopsys Lynx Design System, early tool, IP and flow enablement, and integration roadmap of Lynx, ARM processor and ARM Physical IP for the Common Platform's 32nm/28nm high-k metal-gate (HKMG) process technology.
  • Including worked example of an ARM Cortex™ processor using the latest versions of the Synopsys Lynx Design System and ARM Physical IP in development for the Common Platform™ 32/28LP offering.

  Glenn Dukes, VP of Professional Services, Synopsys, Inc.

Conference Abstracts

Wednesday, October 21st:

High-Performance, Lower-Power, Reduced Route Architecture for the AMBA 3 AXI On-Chip Interconnect
Fred Roberts
Synopsys
10:00 AM - 10:45 AM – Room 203

In a typical system the bandwidth requirements for each interconnecting master and slave varies widely. Some master-slave links have high bandwidth requirements, while others have low latency requirements. Faced with growing demands on system performance it becomes increasingly important to be able to effectively tune the bandwidth allocation for each master-slave link in the system. This presentation details an On-Chip-Bus architecture that enables the setting of bandwidth allocation at each arbitration point with reduced On-Chip-Bus area/power and routing for predefined low performance links.

Optimized Implementation of GHz ARM Cortex-A8 Processor - High performance with Low Power
Daniel Biset
Synopsys
4:00 PM - 4:45 PM – Room 202

Both mobile and tethered devices are requiring increased performance with decreased power consumption. In this session. we'll present how the combination of optimized methodology. tools and physical IP can address these needs. With many design implementations. getting the last 10% performance increase can take 80% or more of the total effort. This classic dilemma wreaks havoc on design schedules and causes the risk averse to limit such uncertain activities. Realizing this. Synopsys and ARM have partnered in a 3-year series of implementation case studies across methodologies. libraries. and process technologies on the ARM Cortex™-A8 processor design. In this latest paper. we discuss a case study targeted at pushing performance for the ARM Cortex-A8 core using ARM DesignStart™ and Enhanced-IP libraries and memories for the TSMC 40G foundry process and the Synopsys Galaxy™ Implementation Platform. The paper describes results using some of the latest 2009.06 DC Topographical and IC Compiler capabilities together with a highly tuned set of user constraints. delivering impressive performance results. The techniques discussed here could be applicable to any high-performance design. Key techniques covered include: library subset usage scenarios. delay performance vs. cell area tradeoffs. cell placement density vs. floorplan dimension tuning. placement bounds overrides for clock and data paths. leakage optimization techniques. signoff optimization between IC Compiler and Prime Time. as well as the usage of the latest clock tree synthesis capabilities together with intelligent user clock constraints. For each technique. we examine the performance and ease of convergence as well as the schedule/turnaround time cost. The author have extensive experience with leading-edge implementations of ARM processor cores. pioneering new techniques and methodologies as well as collaborating to optimize methodology. tools. and IP together for high performance/low power implementations.

Friday, October 23rd:

Increasing Software Development Productivity with ARM and Synopsys Modeling Solutions
Frank Schirrmeister
Synopsys
10:00 AM - 10:45:00 AM – Room 209

This presentation will illustrate how the combination of ARM and Synopsys system-level modeling solutions jointly enable earlier and more productive software development. It will review the key system-level model requirements for software development, architecture exploration and verification along the eight most often cited customer concerns: model speed, time of availability, accuracy, development cost, bring up cost, debug insight, execution control and system interfaces to the environment. The audience will learn how to use ARM processor-based sub-systems in conjunction with Synopsys DesignWare transaction-level models of connectivity IP like SATA, PCI-e and USB in virtual platforms based on the standard OSCI SystemC TLM-2.0 APIs. Special consideration will be given to building virtual platforms in the context of multi-core and low power design. The ARM System Generator tool creates SystemC TLM-2.0 compliant models of ARM processor sub-systems including processors, PrimeCells and bus models, which can be debugged using the ARM RealView solution. Synopsys provides solutions for complete electronic system virtualization including a library of processors, connectivity and bus models. The combined ARM and Synopsys model portfolio addresses more than 50% of total IP market and in combination with Synopsys Innovator SystemC TLM-2.0 tools for platform creation allows designers to significantly cut their project schedules and to start software development 9 to 12 months prior to silicon availability.

Solving Common Power Management Verification Issues in ARM-Based SoCs
Bhanu Kapoor, Mimasic
Shankar Hemmady, Synopsys
ShireeshVerma, Conexant
11:00 AM - 11:45 AM – Room 202

Power management techniques that leverage voltage as a handle are being extensively used in power sensitive designs such as SoCs using ARM Cortex cores. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created. We take a look at some of the main power management verification problems found in such SoCs including issues with reset out of wake up, power connectivity, domain isolation and retention, incorrect power sequencing protocol, level shifting errors, and power state management. We will go over details of each of these issues along with solutions to these issues using verification strategy that involved power-aware simulation, rule-based structural checking, and formal tools.

Optimized Implementation of GHz ARM Cortex-A9 Processor - High Performance, with Low Power
Daniel Biset
Synopsys
1:00 PM - 1:45 PM – Room 202

Both mobile and tethered devices are requiring increased performance with decreased power consumption. In this session. we'll present how the combination of optimized methodology. tools and physical IP can address these needs. With many design implementations. getting the last 10% performance increase can take 80% or more of the total effort. This classic dilemma wreaks havoc on design schedules and causes the risk averse to limit such uncertain activities. Realizing this. Synopsys and ARM have partnered in a 2-year series of implementation case studies across methodologies. libraries. and process technologies on the ARM Cortex™-A9 processor design. In this paper. we discuss our latest case study targeted at pushing performance for the ARM Cortex-A9 core using early access ARM Physical IP libraries and memories for the Common Platform™ 32nm low-power foundry process and the Synopsys Galaxy™ Implementation Platform. The paper describes using some of the latest 2009.06 DC Graphical and IC Compiler capabilities together with a highly tuned set of user constraints. delivering surprising performance. power and area results. The techniques discussed here could be applicable to any high-performance design. Key techniques covered include: library subset usage scenarios. delay performance vs. cell area tradeoffs. cell placement density vs. floorplan dimension tuning. placement bounds overrides for clock and data paths. multi-scenario design optimization. leakage optimization techniques. signoff optimization between IC Compiler and Prime Time. as well as the usage of the latest clock tree synthesis and clock mesh capabilities together with intelligent user clock constraints. For each technique. we examine the performance advantage offered and ease of convergence as well as the schedule/turnaround time cost. The authors have extensive experience with leading-edge implementations of ARM processor cores. pioneering new techniques and methodologies as well as collaborating to optimize methodology. tools. and IP together for high performance/low power implementations.

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