System-Level Catalyst Member 

Tensilica 

Tensilica LogoTensilica’s customizable dataplane processors are at the heart of wireless, multimedia and networking applications, and a growing number of our customers integrate our processors into virtual platforms for early architectural exploration. The Synopsys System-Level Catalyst program is an elegant framework allowing Synopsys and Tensilica to validate interoperability of our models with virtual platform, algorithm development and rapid prototyping solutions.

- Chris Jones, Director of Strategic Alliances at Tensilica



Product Description
Tensilica, Inc., is the leader in customizable dataplane processors for System-on-Chip (SOC) designs. Dataplane Processor Units (DPUs) consist of performance intensive DSP (audio, video, imaging, and baseband signal processing) and embedded RISC processing functions (security, networking, and deeply embedded control).

Tensilica's DPUs offer a unique blend of CPU + DSP strengths and deliver programmability, low power, optimized performance, and small core size. The automated design tools behind all of Tensilica’s application specific processor cores enable rapid customization to meet specific dataplane performance targets. You can configure Tensilica's Xtensa processors to match your application. You can also take it one step further by extending the processor, using our Verilog-like TIE language, to add custom instructions that can give you orders of magnitude performance increases.

Tensilica’s DSPs and processors power top tier semiconductor companies, innovative start-ups, and system OEMs for high-volume products including mobile phones, consumer electronics devices (including portable media players, digital TV, and broadband set top boxes), computers, and storage, networking and communications equipment.

Interoperability Description and Customer Benefit
Tensilica provides customizable dataplane processors. Dataplane Processor Units (DPUs) consist of performance intensive DSP (audio, video, imaging, and baseband signal processing) and embedded RISC processing functions (security, networking, and deeply embedded control). The automated design tools behind all of Tensilica’s application-specific processor cores enable rapid customization to meet specific dataplane performance targets. Models created using Tensilica’s automated design tools can be used in Synopsys Virtualizer as processor models and application specific sub-systems. The interface is established using SystemC APIs, potentially TLM-2.0.

Tell me more about Tensilica and Virtualizer, System Studio.

Flow Diagram

Tensilica Diagram