System-Level Catalyst Program Quotes 

Enabling System Design Interoperability 

"Customers of ARC International's award-winning consumer intellectual property (IP) in the form of vertically integrated solutions, multimedia subsystems and configurable processors often integrate our IP into virtual platforms or FPGA prototypes for early software development and verification. The Synopsys System-Level Catalyst program allows development, validation and maintenance of interoperability between ARC’s models and Synopsys’ virtual platform and rapid prototyping solutions."
-Karl Auker, Director of Strategic Alliances
ARC International

 

“Even the most abstract system model can benefit from implementation-accurate models. Component models generated directly from RTL enable users to leverage the substantial design reuse in today’s advanced SoCs and also guarantee that software developed on the virtual model will work on the actual silicon. The System-Level Catalyst program allows us to ensure that hardware-accurate software models generated using our Carbon Model Studio seamlessly work together with Synopsys’ Innovator virtual platform offerings.”
- Bill Neifert, CTO and VP Business Development
Carbon Design Systems

 

"System-level power analysis and optimization are crucial for today’s consumer and wireless products, enabling up to 75% power reduction versus manual RTL design. The Synopsys System-Level Catalyst program enables the integration of our PowerOpt™ Power-Optimizing High-Level Synthesis with Synopsys virtual platform and algorithm development offerings, allowing joint customers to achieve the lowest-power architecture at the system level where the visibility is highest and the power optimization opportunity is greatest."
-Thomas Blaesi, CEO
ChipVision Design Systems

 

"CoFluent facilitates the adoption of virtual platform technologies as it guides Synopsys Innovator users in their architecture choices even before hardware and software development starts and all component choices are made. CoFluent Studio generates SystemC TLM code from graphics and ANSI C. The generated models can be integrated into Innovator when custom IP models are not available in the DesignWare System-Level Library. Workload models can also be generated to drive Innovator simulations with real use case scenarios when embedded software code has not been developed yet."
-Stephane Leclercq, CEO
CoFluent Design

 

"Standards-based interoperability is a key requirement for our mutual customers. CoWare’s participation in Synopsys System-Level Catalyst program, enables our joint customers to execute the Synopsys DesignWare System-Level Library in our production proven CoWare Platform Architect and CoWare Virtual Platform."
-Tom De Schutter, Marketing Manager, IP Models
CoWare

 

“By offering a library of tool-independent SystemC TLM-2.0 compliant transaction-level models, Synopsys is facilitating the adoption of the new standard and making a valuable contribution to the needs of the SystemC community. Doulos is pleased to be working with Synopsys to enable our customers to benefit from using the Synopsys DesignWare System-Level Library on our industry leading SystemC and TLM-2.0 training classes.”
- John Aynsley, Technical Director
Doulos

 

"Emsys’ USB protocol stack software packages in C and C++ are available for the Synopsys DesignWare® USB solution. Gaining access to virtual platforms representing Synopsys’ USB solutions allows us to start software development and porting at the earliest possible time and to shave off important weeks off our joint customers schedules though early software delivery."
-Karsten Pahnke, CEO
emsys Embedded Systems GmbH

 

"Custom daughter boards for Synopsys HAPS Rapid Prototyping Solutions are important for our customers to customize system interfaces and to integrate existing hardware. The System-Level Catalyst program allows us to get access to Synopsys rapid prototyping related software offerings, enabling Enterpoint’s development services for our joint customers."
-John Adair, Director
Enterpoint Ltd.

 

"Once in a while design methodologies undergo significant changes in abstraction. Design teams today are quickly adapting to achieve better results in less time ultimately pushing them beyond traditional RTL-based design flows. As the shift to ESL methodologies accelerates, product interoperability will be critical. Forte’s Cynthesizer SystemC synthesis customers will benefit from continued standards-based approaches and programs such as the System-Level Catalyst Program.”
-Brett Cline, Vice President, Sales & Marketing
Forte Design Systems

 

"Interoperability and model availability have long been inhibitors for the adoption of system-level design flows. Making system-level model libraries and tools freely available to members as part of the Synopsys System-Level Catalyst program enables further mainstream adoption of ESL solutions."
-Gary Smith, Chief Analyst
Gary Smith EDA

 

"Open standards are crucial to enable growth of a broader ecosystem, and our mutual customers will benefit from the tool-independence of our SystemC models. Synopsys' market position in the IP space made DesignWare System-Level Library a natural choice to distribute our processor models and the System-Level Catalyst program allows our two companies to maintain interoperability between our models and Synopsys’ system-level solutions."
-Mike McGinnis, Program Director of PowerPC Licensing
IBM

 

"The integration of Open Virtual Platforms processor models with the Synopsys Innovator tools provides customers with an expanded set of IP with which to build virtual platforms. Moreover, the native TLM-2.0 interface in the instruction accurate OVP models ensures that users will have the fastest possible simulation performance, as is required for software development on the virtual platform."
-Simon Davidmann, CEO
Imperas

 

"As a leading provider of embedded USB software and drivers, it is critical for Jungo to have access to development platforms, enabling timely and quality software delivery. The Synopsys System-Level Catalyst Program extends our cooperation with Synopsys as we gain access to virtual platforms with system-level models of the Synopsys DesignWare Cores, allowing us to port our USBware™ embedded USB software protocol stack prior to silicon availability of our customer’s devices. Besides time to market improvements, the debug visibility in the Synopsys USB virtual platforms improves development productivity at the hardware/software interface."
-Ophir Herbst, GM Connectivity Software
Jungo

 

"With increased time to market pressure, early start of productive software development becomes instrumental. The Synopsys System-Level Catalyst program enables us to validate tool interoperability of our market leading debug solutions with Synopsys virtual platforms and FPGA prototypes."
-Stephan Lauterbach, General Manager
Lauterbach GmbH

 

“As a leading provider of USB drivers and firmware for high-volume portable devices, MCCI considers time to market a crucial development consideration. Gaining access to virtual platforms of USB IP in the Synopsys DesignWare® System-Level Library as part of the System-Level Catalyst program enables us to develop and demonstrate our solutions prior to silicon availability, significantly improving customer interaction and time to market.”
- Terry Moore, CEO
MCCI

 

"With the increasing share of embedded software as part of chip design projects, traditional hardware verification is undergoing fundamental changes and improvements. The Synopsys System-Level Catalyst program enables NoBug to gain access to Synopsys system-level solutions in order to provide verification related services for the multimedia, telecommunications, networking and computer industries."
-Moshe Shalev, CEO
NoBug

 

"Successful integration of RTL blocks into system level models depends on accurate, consistent adapters. The Synopsys System-Level Catalyst program enables SDV to deliver consistent support for the Synopsys Innovator platform across a variety of co-simulation & co-emulation environments with its combination of auto-generated standard IP, services for custom protocol transactors and customer-enabling TransactorWizard toolset."
-Bernard Deadman, CEO
SDV Ltd.

 

“Ever increasing algorithm complexity, especially in next generation wireless and multimedia systems, requires significant productivity gains in implementation and verification of these systems. Connections of algorithmic synthesis to system-level algorithm verification and optimization solutions as well as virtual platforms addresses those requirements. The Synopsys System-Level Catalyst program is an elegant initiative to allow Synopsys solutions and Synfora’s PICO platform to maintain interoperability to provide an integrated solution to our customers.”
- Vinod Kathail, CTO
Synfora

 

"The system-level market’s growth and our customers' adoption of system-level methodologies have been limited by severe market fragmentation and lack of model and tools interoperability. With the System-Level Catalyst Program Synopsys is helping open up the system-level market to mainstream adoption, enabling new levels of interoperability."
-George Zafiropoulos, Vice President Solutions Marketing
Synopsys

 

"System-on-Chip designs made by our customers are evolving into ‘Seas-of-Cores’, composed of many application-specific processors (ASIPs) with local memory and interconnect structures. By working with Synopsys, and integrating our ASIP design tools with Synopsys’ Innovator technology, our joint customers obtain a more complete ESL tool flow encompassing both virtual system-level modeling and debugging, architectural optimization, and ASIP-based software implementation. Innovator is the leading virtual platform solution. We are pleased to work with Synopsys in this field."
-Gert Goossens, CEO
Target Compiler Technologies

 

“Tensilica’s customizable dataplane processors are at the heart of wireless, multimedia and networking applications, and a growing number of our customers integrate our processors into virtual platforms for early architectural exploration. The Synopsys System-Level Catalyst program is an elegant framework allowing Synopsys and Tensilica to validate interoperability of our models with virtual platform, algorithm development and rapid prototyping solutions.”
- Chris Jones, Director of Strategic Alliances
Tensilica

 

"Recent customer successes adopting our joint solutions underscore the value of standards-based interoperability. Through our mutual support of OSCI, Synopsys and VaST are able to deliver a more integrated, more complete solution for our mutual customers. The System-Level Catalyst program efficiently allows both of our companies to maintain and validate interoperability of our virtual platform solutions to ease customer adoption."
-Jeff Roane, Vice President of Marketing
VaST Systems

 

"VDC expects software design and verification to continue to play an increasingly important role in the hardware and system engineering processes. At the same time, software solution providers are looking for improved methods and tools to enable their customers to program to increasingly complex hardware architectures. Synopsys’ introduction of the System-Level Catalyst program recognizes the necessity for greater collaboration among software and hardware engineering solution companies and the ongoing endeavor of these organizations to provide their customers with the resources required to further advance engineering productivity."
-Matt Volckmann, Senior Analyst/Program Manager
VDC Research’s Embedded Software Practice

 

"We are pleased that Synopsys' Synplicity Business Group is working together with Xilinx to integrate the latest Xilinx devices into their HAPS prototyping systems. The System-Level Catalyst program allows Synopsys and Xilinx to validate interoperability of our hardware and software offerings to ease the adoption of our joint solution by our mutual customers."
-Tom Feist, Senior Marketing Director, ISE Design Suite
Xilinx

 



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