System-Level Catalyst Program 

Enabling System Design Interoperability  

Overview
The System-Level Catalyst Program accelerates the adoption of system-level design.

The purpose of the System-Level Catalyst Program is to promote interoperability between system-level design solutions. To learn how specific System-Level Catalyst members help to increase your design productivity, please visit the appropriate member web page by clicking on the company name below. On each program member's web page you can request specific information regarding the joint design flow.

System-Level Catalyst Program is open to system-level tool vendors, intellectual property (IP) vendors, embedded software companies and service providers, the program is designed to benefit mutual customers by advancing tool and model interoperability as well as availability of system-level models and services.

Members of the System-Level Catalyst Program gain access to Synopsys system-level products for virtual prototyping, architecture development, processor design, algorithm development and hardware prototyping.

System-Level Catalyst Program members may also use the Synopsys System-Level Catalyst logo with their products or services to indicate system-level interoperability.

For more information on the collaboration with each System-Level Catalyst member click on the member's logo below.


IP Models

ARMArterisCarbon Model Studio
MIPSTensilica


System Modeling

CoFluentExperMeta


Specification and Analysis

DoceaSemiforceTasking


Implementation

Forte Design Systems


Software-based Verification

CoverifyeSolSDV
TOOL 


Debugger and Embedded Tools

ACEADaCARM
LauterbachPLSVectorFabrics


Protocol Stacks, OS and Middleware

Emsys


Functional Models

Xilinx


Hardware-assisted Verification

Xilinx  


Education and Services

Circuit SutraDouloshdLab
CVCNoBugVayavya


Standards Partners

AccelleraAutosarOCP
Power8SystemC