Transaction-level testbench development enables users to focus on scenarios, creating better test cases with less effort. Re-useable transactors translate between transaction-level records and protocol-compliant interface signals, and detect protocol violations. SDV’s formally-based transactor generation technology creates optimal support from system level to RTL simulation from the same protocol description and automatically creates functional coverage and transaction-recording features.
SDV provides flexible support for verification methodologies with the TrasactorWizard interface generation tools, ready-to-run transaction interfaces, configurable simulation source code for license-free runtime interfaces, configurable protocol descriptions and full implementation, generation & validation services.
Interoperability Description and Customer Benefit Tell me more about SDV and Virtualizer, System-Level Library.
SDV’s re-useable transactors translate between transaction-level records and protocol-compliant interface signals, and detect protocol violations. Together with Synopsys Virtualizer and DesignWare System-Level Library they allow users to reuse high-level models for RTL verification and software development using hybrids of FPGA prototyping and virtual platforms.