NoBug has been an early adopter of methodologies promoting reuse, interoperability and seamless integration of verification components.
NoBug Verification IPs (VIP) have been implemented in either e or SystemVerilog, using recognized methodologies (eRM, VMM). VIP from NoBug provides for uniform handling of cross-environment concerns, promoting interoperability. The VIPs are ready-to-use, out-of-the-box verification environments, typically focusing on a specific protocol or architecture. Each VIP comprises a complete set of elements for simulating, checking, and collecting coverage information on the device under test (DUT) implementation of the VIP protocol or architecture. It expedites creation of a more efficient test bench for the DUT and can work with both Verilog and VHDL designs. Finally, one can use a VIP as a full verification environment, or add it to an existing environment. There are several types of verification IPs that NoBug has developed; for details visit: http://nobug.ro/products Interoperability Description and Customer Benefit
NoBug is a SystemVerilog Verification IPs provider, and a member of the DesignWare® Verification IP (VIP) Alliance Program, whose VIPs integrate seamlessly with Synopsys’ Virtual Platforms and tools. NoBug also provides services for system-level integration. Tell me more about NoBug and Innovator, System-Level Library.