System-Level Catalyst Member 

ChipVision Design Systems 

ChipVision Logo System-level power analysis and optimization are crucial for today’s consumer and wireless products, enabling up to 75% power reduction versus manual RTL design. The Synopsys System-Level Catalyst program enables the integration of our PowerOpt™ Power-Optimizing High-Level Synthesis with Synopsys virtual platform and algorithm development offerings, allowing joint customers to achieve the lowest-power architecture at the system level where the visibility is highest and the power optimization opportunity is greatest.

- Thomas Blaesi, CEO of ChipVision Design Systems


Product Description
ChipVision’s patented PowerOpt™ power-optimizing high-level synthesis tool is the first design-for-low-power solution that lets designers synthesize power-efficient RTL architectures from the Electronic System Level (ESL), where the most significant power optimization can be achieved. Using PowerOpt, semiconductor developers accurately analyze power consumption at the system level using real activity data, and automatically achieve power savings of up to 75 percent compared to manual RTL design.

PowerOpt software automatically optimizes for low power while synthesizing ANSI C++ and SystemC code into Verilog RTL designs, producing the lowest-power RTL architecture. It optimizes algorithms, data path bit widths, resources, memory accesses, memory configurations, voltage and performance, clock gating and interconnects. The solution also implements leakage power optimizations. Sophisticated power analysis capabilities built into PowerOpt enable designers to interactively trade-off power versus timing and area to make further optimizations to the design. Power constraints for Synopsys Eclypse power flow are output in Unified Power Format (UPF). PowerOpt also produces an RTL test bench that correlates to the system level ESL test bench, and can be used to drive additional power optimization using Synopsys Power Compiler. In addition, PowerOpt generates a detailed microarchitectural specification for the design.

PowerOpt enables designers to explore the design space by interactively trading off between energy consumption, area, and performance (latency). PowerOpt stores each result so that the designer can compare different synthesized architectures to find the optimal power solution very early in the design flow.

PowerOpt is ideal for companies developing mobile communications, networking, consumer, or automotive applications, where extending battery life or reducing cooling requirements is important.

Interoperability Description and Customer Benefit
PowerOpt reads system-level descriptions from Synopsys System Studio and synthesizes them to a power-efficient Verilog RTL architecture. Prior to synthesis, PowerOpt instruments the description and enables the user to run System Studio on the instrumented code in order to collect switching activity data. This data is used to drive PowerOpt’s unique power-optimizing synthesis engine to create the most power-efficient architecture. The design is written out in Verilog RTL format for implementation using Synopsys’ logic synthesis tools. Power constraints for Synopsys Eclypse power flow are output in Unified Power Format (UPF). PowerOpt also produces an RTL test bench that correlates to the system level ESL test bench, and can be used to drive additional power optimization using Synopsys Power Compiler.

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