| With modern day ASICs becoming more and more platform-oriented designs, there is a clear need to have a seamless flow from system level all the way down to physical design. While individual design teams focus on individual tasks (such as system-level modeling, Pre-Silicon verification, FPGA prototyping etc.) a common thread that flows through is the ability to capture various parts of the system at different modeling levels. |
Through the System-Level Catalyst Program, Synopsys enables a greater ecosystem to meet this challenging new phase of semiconductor systems evolution by offering system-level simulation via System Studio and Virtualizer product lines and then provides a means to link them to time-proven Pre-Silicon verification techniques of VMM through TLM and thereafter a link to FPGA prototyping and acceleration.
CVC has been the front runner in SystemVerilog/VMM adoption in the industry right from its first day of development and is excited to become part of System-Level Catalyst program. Our customers have been asking for seamless integration and trainings at all these levels of modeling and verification as their designs grow bigger and bigger. Enabled with system level trainings, our team is able to broaden the reach to mutual customer base more than ever before.
- Srinivasan Venkataramanan, CTO, CVC Pvt. Ltd.
CVC is a design verification company based in Bangalore, India, whose mission is to create a vibrant VLSI ecosystem, aided by a close working relationship with technology partners and enablers. Multiple re-spins of ASICs over the last decade indicate that functional verification deserves a more contemporary and methodical approach than it receives today. This is especially important, as the "verification gap" is an order of magnitude more than the "design gap". While there are several efforts targeting individual pain points of the entire ASIC flow, a holistic approach from system level all the way down to implementation is still evolving.
CVC offers trainings that are high quality, customized corporate trainings on advanced topics in the area of ASIC/FPGA design verification. CVC delivers trainings on topics such as:
- SystemC for modeling
- Advanced FPGA Synthesis
- Verification using SystemVerilog (VSV)
- Do-it Right VMM (DR-VMM)
- SystemC for ASIC Verification
- C++ for ASIC Verification
For complete listing of trainings, visit http://www.cvcblr.com. CVC offers various consulting services in the area of design verification and system-level modeling to help customers adopt and evaluate emerging technologies and they have developed several customized automation solutions that make the adoption of these technologies smoother in customer flows.
Interoperability Description and Customer Benefit:
With TTR (Time to Results) windows shrinking and growing complexity the ability to reuse models across levels of design and verification is key to customer success. Having the ability to demonstrate the value of Virtualizer-based models for Pre-Si verification and the VMM TLM link to Virtualizer and System Studio simulations is vital for mutual customers as they constantly look for reusable means to shorten the TTR. CVC's time proven trainings with extensions to system level will prove critical for the ecosystem and extend the bandwidth of Synopsys's technical arm to reach out to customers for faster turn-around time for such trainings, workshops etc.
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