System-Level Catalyst Member 

Hdlab 
hdLabTLM (Transaction-Level Modeling) is a higher description than RTL. By abstracting away details of communication implementation, data communications between modules are described. From un-timed to cycle-accurate, communication methods supports wide variety of timing information. In this course, participants will learn practical details of modeling techniques based on OSCI TLM-2.0

- H.Tsuzuki, Manager,Techinical Training Service

Product Description

Learn TLM description based on SystemC and basic communication methods in TLM. Synopsys' Platform Architect will be used to introduce participants to system level simulations using TLM.

Target Participants:
Firmware/Software engineers
System architects
Hardware engineers (HDL, SystemC)

Course Outline:
Chapter 1 - Introduction to system modeling & usage examples
Chapter 2 - Required SystemC descriptions for TLM
Chapter 3 - TLM2.0 & payload
Chapter 4 - System environment design using Platform Architect

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