IC design verification has become simultaneously complex and critical. The VMM methodology, defined in the book Verification Methodology Manual for SystemVerilog, provides proven industry best practices developed since 2005. Using VMM enables the creation of robust, reusable, and scalable verification environments using the SystemVerilog language standard. The VMM methodology enables verification engineers to develop powerful transaction-level, constrained-random verification environments. A comprehensive set of guidelines, recommendations, and rules help engineers prevent common mistakes while creating interoperable verification components. The VMM standard library provides the foundation base classes for building advanced testbenches, while the VMM applications provide higher-level functions for improved productivity.
Synopsys donated the source code for its implementation of the VMM methodology to the Accellera standards- setting organization to speed development of verification interoperability standards. Source code and applications for the complete VMM implementation are also freely available as open standards through the Apache 2.0 open source license from www.vmmcentral.org. Synopsys has enabled users and vendors throughout industry to take immediate advantage of years of investment in the VMM methodology.
In response to the increasing need for targeted verification of low-power IC designs, the book Verification Methodology Manual for Low Power Design (VMM-LP) addresses all aspects of functional verification for designs employing power management plans and techniques. Synopsys’ corresponding implementation of the VMM-LP base class library is freely available as an open standard under Apache 2.0 open source licensing from www.vmmcentral.org.
Synopsys support for VMM
As a leader in verification, Synopsys provides support for the VMM and VMM-LP standard methodologies throughout its solutions, Discovery verification platform, tools, and IP.