Interconnect Technology Format (ITF) 

Modeling the interconnect parasitic effects 

Synopsys' Interconnect Technology Format (ITF) provides detailed modeling of interconnect parasitic effects that enables designers to perform accurate parasitic extraction for timing, signal integrity, power and reliability signoff analysis. ITF offers a flexible and innovative format to accurately model the effects of increased process variation at advanced process technologies. ITF has been evolving for more than 10 years and is the semiconductor industry’s most widely used interconnect modeling format. It is supported by leading semiconductor foundries and integrated device manufacturers, and is proven on thousands of production designs.

ITF License Information
An ITF license gives the licensee the right to use the format to describe the modeling of interconnect parasitic effects for a process technology. For an EDA vendor, an ITF license allows the vendor to develop tools to read the ITF modeling data. For an ASIC or IP vendor, it allows them to write internal applications to read the ITF data and distribute any parasitic data to their customers and the EDA vendors who have licensed ITF. Similarly, in a university, an ITF license allows it to develop applications to read in the ITF modeling data. All ITF licensees receive documentation and information on format updates.

How To Become an ITF Licensee
The open source license for ITF is free and available now. View the license agreement. To download, Register Now! to receive your password and login codes.

Contact Us
For additional information regarding ITF and the TAP-in program, please contact us at the following:
ITF Information and Support
TAP-in Program Information