SystemVerilog Catalyst 

Promoting the industry's unified HDVL standard 

Synopsys' SystemVerilog Catalyst program promotes the development and use of EDA tools, verification IP, and training services which support the SystemVerilog standard language for design and verification.

Members of the SystemVerilog Catalyst Program may gain access to Synopsys’ tools, platforms, and solutions which support the SystemVerilog standard. This access allows development of products and services that are interoperable with Synopsys’ offerings while providing support for mutual customers.

Members