ARC Access Program Member 

Ashling Microsystems Ltd. 
Ashling Logo Ashling Microsystems Ltd., an SFO Technologies company, has over 25 years experience in Embedded Development. Ashling is a world leader in embedded development tools and embedded engineering services with a reputation for quality, reliability and outstanding customer support.

Ashling’s Opella-XD for ARC Debug Probe is a powerful JTAG Debug Probe for embedded development with Synopsys ARC configurable RISC cores.

Developed in co-operation with Synopsys, the Opella-XD Debug Probe integrates with the MetaWare IDE and provides powerful run/stop debug control. Opella-XD is also supplied with the Ashling GDB Server which allows you to connect to your embedded target and debug using the GNU GDB debugger.

Opella-XD connects to your host PC via USB2.0 and provides very fast code download (>3MB/s) to the target ARC system. Opella-XD works on both Windows and Linux hosted platforms.

Advanced features of Opella-XD include:
  • Fast, easy-to-install USB 2.0 High-Speed Interface (480Mb/s)
  • Supports all popular hardware debug protocols
  • Unique Auto-conditioning Probe provides maximum possible download speed to target with fastest JTAG clock frequencies
  • Hot-plug support allows post-mortem debugging
  • Fast, trouble-free Plug-and-Play installation
  • Supplied with 20-pin Target Probe Assembly for Debug interface to target device or target
  • FPGA.
  • Optional 15-pin D-Type JTAG adapter for Debug interface to target device
  • Opella-XD supports FPGA Programming on ARC FPGA targets or user’s target board
  • Wide target voltage range: 0.9V to 3.6V
  • Versatile Target-Reset and Test-Port-Reset support
  • Built-in diagnostics instantly show status of Target, Debug Probe and USB link
Opella-XD Debug Probe Specification:
  • High-speed USB2.0 (480Mb/s) interface to host PC
  • Target JTAG clock rates up to 100MHz
  • Auto-conditioning for fast JTAG clock frequencies
  • Configurable Target-Reset and Test-Port-Reset, under full user control
  • Fine-grained adjustment of JTAG clock frequency from 1KHz to 100MHz
  • Supports target operating voltages from 0.9V to 3.6V. Opella-XD detects and automatically configures for the appropriate target voltage.
  • Hot-plug support; allows connection to a running target without resetting or halting
  • Fully powered by USB interface; no external power-supply needed
  • Display/read/write of target system memory and peripheral registers
  • Support for all on-chip hardware breakpoints; unlimited software breakpoints
  • Target Reset control and Remote Reset detect
  • Run/stop control of target application including go, halt, step over, step into and step out of
  • Operates with Synopsys MetaWare Development Toolkit or GNU GDB Debuggers under Windows or Linux based hosts
  • Support for Multi-core debug
  • Support for multiple Opella connected to the same PC (this supports Multi-core systems where each core has a unique JTAG interface)

ARC-specific Support Details
All DesignWare® ARC® cores are supported.

Learn more about how Ashling and Synopsys work together.

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