Webinars 


SpyGlass New Feature Update (Japanese)
Learn about the latest key feature updates for the SpyGlass version 5.5.0 and 5.6.0 family of products including SpyGlass Lint, SpyGlass CDC, SpyGlass Constraints, SpyGlass Power, and SpyGlass DFT.
Kenichi Komiya, Verification CAE, Synopsys
Jun 01, 2016

Make your Coverage Closure SMARTer with Verdi – A Primer on Verification Planning and Coverage Modeling
In Part I of a multi-part webinar series on Verification Planning and Coverage, we will focus on how verification planning using Verdi Coverage can help make your coverage closure goals SMART.
Vaishnav Gorur, Product Marketing Manager, Verification Group & Bart Thielges CAE, Coverage and Planning, Verification Group, Synopsys
May 18, 2016

Xilinx and Synopsys Present: Meeting Test Goals Faster with SpyGlass DFT ADV
Early detection of testability issues can prevent major bottlenecks downstream and avoid time-consuming design iterations. In this webinar, Synopsys presents new techniques and capabilities available in SpyGlass DFT ADV such as high-impact test points to boost coverage, reduce the number of patterns, and minimize test costs. Our guest speaker from Xilinx discusses test challenges associated with large SoC designs such as the Xilinx Zynq® UltraScale™ chip family, and illustrates how SpyGlass DFT ADV addresses testability issues early in the design flow, saving weeks of complex DFT-related ECOs.
Amit Majumdar, Principal Engineer, Xilinx; Anthony Joseph, Applications Engineer, Synopsys; Dmitry Melnik, Marketing Manager, Synopsys
Apr 28, 2016

Custom Compiler-Visually-assisted Automation for Custom Layout
Learn about Synopsys' new full-custom solution that features a visually-assisted automation flow tuned for FinFET-based designs to speed up common design tasks, reduce iterations and enable reuse.
Chris Shaw, Technical Marketing Manager, Synopsys Fred Sendig, Synopsys Fellow, Synopsys
Apr 21, 2016

Increasing Verification Closure Effectiveness with Formal Verification
Learn about Synopsys VC Formal advanced techniques and formal coverage metrics that provide better convergence and simulation-like visibility, to achieve formal verification signoff.
Prapanna Tiwari, Formal Verification Product Marketing, Synopsys; Sean Safarpour, Ph.D., Formal Verification CAE Manager, Synopsys
Apr 20, 2016

Successful SoC Implementation of USB Type-C and DisplayPort Alt Mode
This webinar discusses how to integrate USB Type-C and DisplayPort functionality, including solving critical hardware and software partitioning challenges.
Morten Christiansen, Technical Marketing Manager, Synopsys; Gervais Fong, Senior Product Manager, Synopsys
Apr 19, 2016

Securing IoT Systems with a Root of Trust
Security is critical to the success of IoT SoCs and must be an early design consideration. This webinar discusses IoT security threats and use cases requiring a secure root of trust.
Mike Borza, Member of Technical Staff, Synopsys
Apr 14, 2016

Better Testing Through Automation and Continuous Integration with Virtualizer Development Kits
This webinar introduces how simulation-based Virtualizer Development Kits are the perfect technology to enable the integration and testing of hardware dependent software in a continuous manner.
Victor Reyes, Technical Marketing Manager, Synopsys
Apr 13, 2016

Test & Repair of SoCs for Functional Safety Applications
Learn about diagnosis, debug and self-test and repair solutions for memories, logic, AMS and interface IP blocks for automotive requirements to satisfy key criteria like low DPPM.
Yervant Zorian, Fellow & Chief Architect, Synopsys; Faisal Goriawalla, Product Marketing Manager, Synopsys
Apr 12, 2016

Evolution of Socionext’s Golden UPF Design Flow for Achieving Power Efficiency
Learn about Socionext’s ever-evolving UPF design flow and their experience with successfully deploying a Golden UPF-based methodology using Synopsys tools.
Mahiro Hikita, Manager, Design Department II, SoC Design Division, Socionext, Inc.
Apr 07, 2016

Evolution of Socionext’s Golden UPF Design Flow for Achieving Power Efficiency (Japanese)
Learn about Socionext’s ever-evolving UPF design flow and their experience with successfully deploying a Golden UPF-based methodology using Synopsys tools.
Mahiro Hikita, Manager, Design Department II, SoC Design Division, Socionext, Inc.
Apr 07, 2016

Accelerate your FPGA Design Schedules with Synplify Premier
This webinar will detail how Synplify Premier supports each design phase through improvements in automation, constraint setup, technologies for the best timing QoR and debugger information.
Paul Owens, Senior Corporate Applications Engineer, Synopsys
Mar 23, 2016

Bridging the Gap in Mixed-Signal Debug: Introducing Synopsys' NEW Verdi Advanced AMS Debug Solution
In this webinar, we will demonstrate how Synopsys' new Verdi Advanced AMS debug solution, based on the market-leading Verdi SoC debug platform, delivers groundbreaking co-simulation debug for both analog and digital engineers, as well as system integrators.
Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys; Vaishnav Gorur, Product Marketing Manager, Verification Group, Synopsys
Mar 15, 2016

TSMC and Synopsys: 10nm Physical Verification Enablement for IC Validator
Learn about TSMC’s 10nm design enablement readiness & the tooling supported in their physical design flow; Synopsys will cover new technologies addressing the challenges of 10nm design verification.
Captain Liu, Manager, Design Methodology and Service Marketing TSMC; Ron Duncan, Sr. CAE Manager, Synopsys
Mar 03, 2016

Design, Test & Repair Methodology for FinFET-based Memories
Understand the challenges associated with testing FinFET-based memories and new methods to address FinFET-specific defects.
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys
Mar 03, 2016

How Flexible Debug Can Speed Physical Prototype Bring-Up and Software Development
This webinar will provide an overview of the wide spectrum of critical debug techniques for efficient FPGA-based prototype bring-up, embedded software development and hardware/software integration.
Achim Nohl, Technical Marketing Manager, Synopsys
Mar 02, 2016

Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Jack Ting, CAE, Synopsys; Manoz Palaparthi, Technical Marketing Manager, Synopsys
Feb 24, 2016

Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis (Traditional Chinese)
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Martin Liu, CAD Engineer, Sunplus Technology
Feb 24, 2016

Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis (Simplified Chinese)
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Martin Liu, CAD Engineer, Sunplus Technology
Feb 24, 2016

What’s Next in Storage: NVMe Verification IP
In this webinar, we will discuss the latest technology in storage protocols, NVMe, a rapidly evolving high performance storage standard developed to reduce latency and support parallelism.
Eric Peterson, Senior R&D Engineer, Synopsys; Paul Graykowski, Senior Corporate Application Engineer (CAE) for Verification Group, Synopsys
Feb 23, 2016

Improving Analog Verification Productivity Using Synopsys Simulation and Analysis Environment (SAE)
Learn about the comprehensive GUI-based transistor-level simulation and analysis environment that is deeply integrated with CustomSim, FineSim, and HSPICE circuit simulators.
Deepa Kannan, SAE Technical Marketing Manager, Synopsys
Feb 17, 2016

Accelerate Interface IP Integration for Faster Time-to-Market
This webinar uses case studies to address the challenges of integrating IP into an SoC, optimizing IP subsystem architecture, and simplifying IP subsystem verification.
Ralph Grundler, Product Marketing Manager for DesignWare IP Prototyping Kits and IP Subsystems, Synopsys
Feb 10, 2016

Synopsys and TSMC Get Smart with Bluetooth for IoT SoCs
Learn about the growing IoT market trends, the required wireless connectivity and new process technologies to achieve low-power consumption and enable efficient connectivity between devices.
Manuel Mota, Technical Marketing Manager, Synopsys; Leon Chang, Program Manager, TSMC
Feb 03, 2016

Sunplus Technology Perspective: Achieving Superior Results and Shorter Schedules with Design Compiler (Traditional Chinese)
Maximizing IC performance and reducing area are key for Sunplus to deliver competitive and cost-effective multimedia products to market while meeting aggressive schedules. In this webinar, John Yeh CAD engineer will discuss how Sunplus uses the latest Design Compiler technologies to improve predictability, reduce schedules and achieve superior results. He will show how DC Explorer helps speed up the development of high quality RTL and constraints and allows early physical exploration. He will also discuss how Design Compiler Graphical enables Sunplus to achieve higher performance and tighter correlation to IC Compiler for faster design convergence.
John Yeh, CAD Engineer, Sunplus Technology
Jan 28, 2016




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