Webinars 


How Flexible Debug Can Speed Physical Prototype Bring-Up and Software Development
This webinar will provide an overview of the wide spectrum of critical debug techniques for efficient FPGA-based prototype bring-up, embedded software development and hardware/software integration.
Achim Nohl, Technical Marketing Manager, Synopsys
Mar 02, 2016

Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Jack Ting, CAE, Synopsys; Manoz Palaparthi, Technical Marketing Manager, Synopsys
Feb 24, 2016

Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis (Traditional Chinese)
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Martin Liu, CAD Engineer, Sunplus Technology
Feb 24, 2016

Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis (Simplified Chinese)
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Martin Liu, CAD Engineer, Sunplus Technology
Feb 24, 2016

Improving Analog Verification Productivity Using Synopsys Simulation and Analysis Environment (SAE)
Learn about the comprehensive GUI-based transistor-level simulation and analysis environment that is deeply integrated with CustomSim, FineSim, and HSPICE circuit simulators.
Deepa Kannan, SAE Technical Marketing Manager, Synopsys
Feb 17, 2016

Accelerate Interface IP Integration for Faster Time-to-Market
This webinar uses case studies to address the challenges of integrating IP into an SoC, optimizing IP subsystem architecture, and simplifying IP subsystem verification.
Ralph Grundler, Product Marketing Manager for DesignWare IP Prototyping Kits and IP Subsystems, Synopsys
Feb 10, 2016

Synopsys and TSMC Get Smart with Bluetooth for IoT SoCs
Learn about the growing IoT market trends, the required wireless connectivity and new process technologies to achieve low-power consumption and enable efficient connectivity between devices.
Manuel Mota, Technical Marketing Manager, Synopsys; Leon Chang, Program Manager, TSMC
Feb 03, 2016

Sunplus Technology Perspective: Achieving Superior Results and Shorter Schedules with Design Compiler (Traditional Chinese)
Maximizing IC performance and reducing area are key for Sunplus to deliver competitive and cost-effective multimedia products to market while meeting aggressive schedules. In this webinar, John Yeh CAD engineer will discuss how Sunplus uses the latest Design Compiler technologies to improve predictability, reduce schedules and achieve superior results. He will show how DC Explorer helps speed up the development of high quality RTL and constraints and allows early physical exploration. He will also discuss how Design Compiler Graphical enables Sunplus to achieve higher performance and tighter correlation to IC Compiler for faster design convergence.
John Yeh, CAD Engineer, Sunplus Technology
Jan 28, 2016

Sunplus Technology Perspective: Achieving Superior Results and Shorter Schedules with Design Compiler (Simplified Chinese)
Maximizing IC performance and reducing area are key for Sunplus to deliver competitive and cost-effective multimedia products to market while meeting aggressive schedules. In this webinar, John Yeh CAD engineer will discuss how Sunplus uses the latest Design Compiler technologies to improve predictability, reduce schedules and achieve superior results. He will show how DC Explorer helps speed up the development of high quality RTL and constraints and allows early physical exploration. He will also discuss how Design Compiler Graphical enables Sunplus to achieve higher performance and tighter correlation to IC Compiler for faster design convergence.
John Yeh, CAD engineer, Sunplus Technology
Jan 28, 2016

Synopsys Mixed-Signal IP Designers Achieve Increased Productivity Using Enhanced StarRC Netlist Reduction
Learn about StarRC's recent enhancements in RC netlist reduction & how these improvements are helping Synopsys IP developers verify the performance & integrity of their industry-leading IP portfolio.
Sunderarajan S. Mohan, Architect, Analog and Mixed Signal Circuits, Synopsys; Changli Guo, R&D Manager for Extraction Products, Synopsys
Jan 27, 2016

Catching the Uncatchable Bugs with SpyGlass CDC: Comprehensive, Practical, and Powerful Analysis
In this webinar, we will discuss how the SpyGlass CDC solution enables comprehensive clock and reset domain crossing (CDC/RDC) verification for more than a billion gates, helping designers to avoid costly chip killer bugs, re-spins and achieve signoff quality verification.
Kiran Vittal, Director Product Marketing, Verification Group, Synopsys; Sean O’Donohue; Senior Corporate Application Engineer (CAE), Verification Group, Synopsys
Jan 26, 2016

Tackle the Complexities of FinFET Library Characterization with SiliconSmart
This webinar will cover the new, innovative SiliconSmart capabilities that will enable you to work smarter in solving your toughest FinFET library characterization challenges.
Ed Lechner, Director of Marketing, Design Analysis and Sign-off Tools, Synopsys
Jan 13, 2016

Raising Design and Verification Productivity with SpyGlass Lint Advanced: The Next Generation of Lint
In this webinar, we will discuss how the newly introduced SpyGlass Lint Advanced solution identifies RTL issues at their source, pinpoints structural, coding and consistency problems in the RTL descriptions, and helps designers resolve issues quickly before design implementation.
Arbind Kumar Rohilla, Verification Group, Synopsys
Dec 08, 2015

Securing Your IoT Processor Based System
This webinar will provide insight into IoT edge device security requirements and how they can be met with an ultra-low power processor.
Angela Raucher, Product Line Manager, ARC EM Processors, Synopsys
Dec 03, 2015

Impact of IP Reliability, Functional Safety & Quality in Automotive ADAS SoCs
Learn about ISO 26262 and AEC Q100 standards; latency, power, reliability and process-related design challenges; and how certified IP helps ensure functional safety, reliability and quality management.
Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys
Dec 02, 2015

Configure, Integrate & Prototype IP in Minutes (Mandarin)
IP blocks alone can't address designers' growing SoC design & integration challenges. Learn how DesignWare IP Prototyping Kits ease IP configuration & integration and accelerate software development.
Qi Wang, Senior FAE, Synopsys
Dec 01, 2015

Optimizing Quality-of-Service (QoS) with Interconnect and Memory Subsystem Analysis
Sponsored by Synopsys and Arteris, this webinar illustrates how virtual prototyping tools and high-level architecture models provide SoC architects with deep, system-level analysis.
Pat Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys; Alexis Boutillier, Senior Corporate Applications Engineer, Arteris
Nov 19, 2015

A Holistic Approach to Verification: Synopsys VIP for ARM AMBA Cache Coherent Interconnects
In this webinar, we will discuss how to take advantage of the system-level capabilities of Synopsys Verification IP for ARM® AMBA® protocols to verify cache-coherent interconnects. Synopsys VIP includes system-level interconnect test suites and system-level coverage to accelerate verification closure.
Satyapriya Acharya, Engineering Manager, Verification Group, Synopsys
Nov 18, 2015

PrimeTime POCV FinFET Designs - the NVIDIA Experience (Simplified Chinese)
Synopsys will review the PrimeTime POCV technology that helps designers reduce design margins in FinFET designs, and you will learn about NVIDIA’s latest FinFET tapeout experience with PrimeTime POCV.
James Chuang, Senior Technical Marketing Manager, Synopsys
Nov 17, 2015

PrimeTime POCV FinFET Designs - the NVIDIA Experience (Traditional Chinese)
Synopsys will review the PrimeTime POCV technology that helps designers reduce design margins in FinFET designs, and you will learn about NVIDIA’s latest FinFET tapeout experience with PrimeTime POCV.
James Chuang, Senior Technical Marketing Manager, Synopsys
Nov 17, 2015

Enabling Automotive IC Design Reliability
In this webinar, we introduce the challenges facing of designers of high-reliability ICs for the automotive market, and discuss some of the proven Galaxy Design Platform IC implementation and sign-off solutions being deployed by automotive design teams worldwide.
Steve Smith, Senior Director of Marketing, Automotive Solutions
Nov 12, 2015

Building Highly Reliable FPGA Designs for Applications Needing Functional Safety
In this webinar you will learn how to automatically "build in" high reliability using Synopsys Synplify Premier FPGA design tools.
Sharath Duraiswami, Senior Corporate Applications Engineer, Synopsys
Nov 11, 2015

Software is eating the World: End-to-End Prototyping to the Rescue
Co-hosted by Chris Rommel of VDC, this webinar will explore the value between prototyping methods and their benefits for enabling early architecture exploration, software development, hardware-software integration and system validation.
Tom De Schutter, Senior Product Marketing Manager, Synopsys; Chris Rommel, Executive Vice President, IoT& Embedded Technology, VDC
Nov 04, 2015

Keeping Pace with Memory Technology using Advanced Verification
In this Webinar, we will review the evolution of memory technology leading to the latest development in DDR, LPDDR, eMMC, High Bandwidth Memory (HBM) and Hybrid Memory Cube (HMC). We will highlight key concerns in the verification of these protocols, and their contributing concerns to overall System Validation. Finally, we will review successful methodologies and techniques that assure project success.
Nasib Naser, PhD. Senior Staff Corporate Applications, Verification Group, Synopsys
Oct 29, 2015