| Advanced-node Custom Layout Using the Laker Custom IC Solution |
Learn about Laker’s rule-based layout, schematic-driven layout, and pattern-based multi-device layout features--ideal solutions for those seeking to improve custom layout productivity at 20-nm and below.
Neel Gopalin, Corporate Applications Engineer, Synopsys; Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys
May 30, 2013 |
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| Verilog-to-Verilog Equivalence Checking Using ESP |
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.
Philip Schmidt, R&D Manager, Synopsys; Dave Hedges, Corporate Applications Engineer, Synopsys
May 29, 2013 |
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| Samsung Foundry and Synopsys Discuss Enabling 14-nm FinFET Design |
Samsung Foundry and Synopsys present the challenges and opportunities of manufacturing with Samsung's 14-nm FinFET process and how these changes impact design enablement.
Dr. Kuang-Kuo Lin, Director, Foundry Design Enablement, Samsung Semiconductor Inc. (SSI); Dr. Henry Sheng, Senior Director of R&D, Synopsys
May 28, 2013 |
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| TSMC and Synopsys Present: DFTMAX Compression, Hierarchical Test and iJTAG |
As the complexity of systems-on-chip increases, so does the need to leverage standards-based methodologies to implement test in a hierarchical manner, across multiple cores.
Dr. Saman Adham, Senior Manager, TSMC; Robert Ruiz, Product Marketing Manager, Synopsys; Adam Cron, Principal Engineer, Synopsys
May 23, 2013 |
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| Transaction Debug with Verdi3 |
In this webinar, you'll learn how to maximize your productivity by using Verdi's Transaction Debugging technology to dump, visualize and trace transactions. You'll learn how the tool's vertical correlation allows you to take the debug to the signal level waveform while retaining all of the necessary debugging details.
Rich Chang, Product Marketing Manager for Debug, Synopsys
May 22, 2013 |
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| Discovery-AMS for Mixed-Signal Verification - An ST-Ericsson Case Study |
ST-Ericsson shares details on how they leveraged new Discovery-AMS multi-core technology to improve their overall verification flow.
Francois Ravatin, AMS Verification Engineer, ST-Ericsson; Helene Thibieroz, Sr. Product Marketing Manager, Synopsys
May 21, 2013 |
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| Conquering HSPA+ Modem Design |
To understand the design flow and provide an introduction to InterDigital’s HSPA+ modem IP.
William Lawton, Senior Manager, InterDigital Communications;
Vafa Ghazi-Moghadam, Staff R&D Engineer, Synopsys
May 15, 2013 |
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| 3 Easy Ways to Accelerate Development of your Embedded SoC |
In this webinar we will show you 3 easy ways to accelerate development time for your embedded SoC software with the DesignWare ARC EM Starter Kit.
Paul Garden, Product Marketing Manager, Synopsys
May 14, 2013 |
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| Achieving Predictable and Highly Reliable 10G Backplane Designs |
This webinar explores the challenges of implementing 10G backplane systems. The webinar walks through a case study and explores techniques that help designers meet stringent backplane requirements.
David Rennie, Senior Analog Design Engineer for Mixed-Signal Interface IP, Synopsys
May 09, 2013 |
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| Late-Stage Leakage Recovery using the Lynx Design System |
The rate of increase in SoC design complexity continues to challenge even the most experienced design teams. Synopsys’ Lynx Design System can help manage many of these complexities. This webinar will discuss strategies that leverage Final Stage Leakage-Power Recovery (FSLR) in IC Compiler, the new PrimeTime ECO Leakage flow and multi-channel libraries to recover leakage power late in the design cycle. These methodologies, as a part of a complete RTL-to-GDSII design solution available in Lynx, can help you achieve your power targets while maintaining design performance. These capabilities will be shown live in a short demo.
Devin Bright, Synopsys
May 08, 2013 |
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| Case Study: Design and FPGA-Prototyping of an Application Specific Processor for Embedded Vision |
This webinar introduces Synopsys’ Vision Processor Design and Prototyping solution, featuring Processor Designer and HAPS FPGA-prototyping.
Drew Taussig, Corporate Applications Engineer, Synopsys
May 07, 2013 |
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| Ease Debug and Control of Network Software Using Virtual Prototypes to Do Full System Simulation |
Learn how you can use a virtual prototype with a DesignWare Gigabit Ethernet model and ARM Cortex-A processor models to simulate a network application like e.g. a server farm.
Robert Kaye, Technical Specialist, ARM; Tom De Schutter, Product Marketing Manager, Synopsys
May 02, 2013 |
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| Implementing Ethernet QoS for use in Automotive Networking Designs |
Learn about Ethernet in automotive designs, Audio Video Bridging (AVB), the driving forces and predictions for Ethernet in the automotive market, and Synopsys’ DesignWare Ethernet QoS IP solution.
John Swanson, Product Line Manager, DesignWare Ethernet IP, Synopsys
May 01, 2013 |
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| New Features and Updates: Sentaurus TCAD (H-2013.03) |
Learn about the new features and enhancements in our H-2013.03 release of Sentaurus TCAD products . Continuing with our effort to enable modeling of technologies at the cutting edge of both, More-Moore and More-than-Moore technologies, we have recently introduced new features and model enhancements for FinFETs and alternative channel transistors, high power wide-band-gap devices and opto-electronics.
Karim El Sayed, Director, TCAD R&D, Synopsys; Sudarshan Krishnamoorthy, TCAD Technical Marketing Manager, Synopsys
Apr 30, 2013 |
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| Optimizing and Validating the Performance of Your AMBA®4 Interconnect |
Learn how to use Synopsys Platform Architect to drive performance criteria that can now be verified in the functional verification process through tight integration with Synopsys Verification IP.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
Apr 25, 2013 |
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| A Hierarchical, Low Power Design Approach for Gigascale Designs |
This webinar will help you understand the best practices for implementation of a Multi-Voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Apr 24, 2013 |
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| What, Where, Who? Integrating Audio Analog Functionality into SoCs (Mandarin) |
Learn what performance trends to consider, where in the system to integrate audio, what challenges are associated with integrating audio in advanced nodes and who to consider in a make vs buy decision.
Ben U, Senior Manager of Analog Design, Synopsys
Apr 10, 2013 |
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| Verifying Advanced Low Power Designs: Find Design-Killing LP Bugs Early and Easily |
Learn how VCS with MVSIM Native Low Power provide the accuracy and comprehensive LP support needed at RTL, and enable LP bugs to be found and fixed early and easily in the design cycle.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Aditya Kher, Senior Corporate Application Engineer (CAE), Low Power Verification, Synopsys; Harsh Chilwal, Senior R&D Engineer, Synopsys
Apr 04, 2013 |
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| Logic Libraries for High-Performance, Processor-Based, Energy-Efficient SoCs |
Learn about ways to maximize system performance while managing power budgets of CPU, GPU, and other SoC blocks, each with different performance/power/area targets.
Ken Brock, Product Marketing Manager, Logic Libraries, Synopsys
Apr 02, 2013 |
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| Reducing Multi-mode STA Turnaround Time with PrimeTime Mode Merging - LSI Case Study |
This webinar will introduce new PrimeTime technology to help design teams manage scenario increases by merging modes. LSI will discuss how PrimeTime mode merging allows them to reduce timing analysis.
Harish Aepala, Principal Methodology Engineer, LSI; Srinivas Muddagowni, Corporate Applications Engineer, Synopsys
Mar 27, 2013 |
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| Accelerate PCIe Integration Testing with Next-Generation Discovery VIP |
Learn an optimal strategy for integration testing using UVM in conjunction with next-generation features of PCIe VIP for more efficient test development, error injection and debug.
Neill Mullinger, Product Marketing Manager, Synopsys; Paul Graykowski, Corporate Application Engineer (CAE), Synopsys
Mar 20, 2013 |
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| Designing with FinFETs |
Learn about the benefits and challenges of transitioning from planar to FinFET technologies and their implications for IP design.
Jamil Kawa, Group Director, Solutions Group, Synopsys
Mar 14, 2013 |
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| Recover Leakage and Maintain Signoff Timing Using PrimeTime ECO - Simplified Mandarin |
This webinar will introduce new PrimeTime ECO technology designed to reduce leakage power while maintaining signoff QoR. We’ll share customer data from Samsung and STMicroelectronics.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; James Chuang, Technical Marketing Manager, Implementation Group, Synopsys
Mar 12, 2013 |
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| Recover Leakage and Maintain Signoff Timing Using PrimeTime ECO - Traditional Mandarin |
This webinar will introduce new PrimeTime ECO technology designed to reduce leakage power while maintaining signoff QoR. We’ll share customer data from Samsung and STMicroelectronics.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; James Chuang, Technical Marketing Manager, Implementation Group, Synopsys
Mar 12, 2013 |
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