Optimizing DSP cores for Performance & Power with DW Logic Libraries & Embedded Memories (Mandarin)
Learn how optimized embedded memories & logic libraries enable your DSP design to achieve performance/power/area targets, and how choosing the correct IP/methodology avoids physical design bottlenecks.
Wendy Chen, IP Program Manager, Synopsys; Dennis Han, Senior Technical Support Engineer, CEVA
Oct 21, 2014

Designing with Non-Volatile Memory for High-Volume Automotive ICs (Mandarin)
Learn about the challenges with designing high-volume automotive ICs and the associated non-volatile memory requirements for high performance, high reliability, and optimized area.
Ming Han, FAE, Synopsys; Ting-Jia Hu, Senior Program Manager, Synopsys
Oct 17, 2014

Reinventing Coverage and Planning with Verdi—A Fully Integrated, Complete Verification Closure Flow To Help You Deliver Chips On Time
The Synopsys Verdi® Coverage solution provides comprehensive planning and coverage analysis technologies as a part of the industry-leading Verdi3™Automated Debug System. We'll discuss why Synopsys' native integration of planning, coverage, and debug technologies provide a complete closure solution to help meet demanding schedules and provide teams with more confidence when asked the inevitable question: '"Are we done yet?"
Steve Chappell, Senior Product Marketing Manager, Debug and Analysis, Synopsys; Michael Horn, Verification Technologist, Synopsys
Oct 14, 2014

Accelerating Coverage Closure by Complementing Simulation with Formal Verification
VC Formal’s unreachable coverage analysis capability can help verification teams save weeks of manual effort, and VC Formal’s SoC connectivity checking capability can help eliminate the very real likelihood of missed bugs using traditional methods of verifying the huge numbers of top-level and block-level connections. We will describe how VC Formal’s capabilities can be easily used for saving time and effort in these very common and important use cases. In this webinar, we will show two crucial areas where formal tools can quickly save time and effort in helping you meet your verification coverage goals.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Anders Nordstrom, Corporate Application Engineer (CAE), Verification, Synopsys; Xiaolin Chen, Corporate Application Engineer (CAE), Verification, Synopsys
Oct 07, 2014

How Reliable is Your FPGA Design? Tips and Tricks for Building-in High Reliability
Learn how to automatically "build in" high reliability using Synopsys Synplify Premier FPGA design tool.
Sharath Duraiswami, Senior Corporate Applications Engineer, Synopsys
Oct 02, 2014

Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO
Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO's latest power recovery technology.
Vivek Ghante, Senior Corporate Applications Engineer, Synopsys; James Chuang, Technical Marketing Manager, Synopsys
Oct 01, 2014

Addressing IP Compliance Challenges with UVM-based Test Suites
Protocol verification is a massive time- and resource-consuming endeavor, fraught with complexity and the risk of errors and omissions. Synopsys Verification Test Suites leverage the expertise of protocol experts to provide a rapidly deployable and extensible set of comprehensive tests, written in easily modifiable and reusable SystemVerilog UVM source code. The webinar will give an overview of the architecture and scope of Synopsys’ Verification Test Suites to achieve faster and higher quality coverage closure.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Karim Aoua, Staff CAE, Synopsys
Sep 30, 2014

UMC and Synopsys: A Complete and Differentiated 28nm Signoff and Manufacturing Infrastructure
This webinar covers the benefits of In-Design, an integrated methodology enabling you to run foundry signoff DRC and Metal Fill runsets inside the place-and-route environment, as UMC and Synopsys share their proven design flow for 28nm chip design.
Anderson Huang, UMC; Dr. Daw Hsu, Synopsys
Sep 25, 2014

Ethernet in the Connected World
In the connected world, data management and robust networking is essential. Learn about new networking demands for data management between connected devices, market trends and IEEE standards.
John A. Swanson, Product Line Manager, Synopsys
Sep 23, 2014

How to Develop Ultra-Low Power Voice Control and Sensor Devices for Always-On IoT Apps
Learn how the efficient response and low power consumption of the ARC® EM DSP processor and Sensory TrulyHandsfree™ software solution deliver excellent performance with long battery life for IoT apps.
Paul Garden, Product Marketing Manager, Synopsys; Bernard Brafman, Vice President of Business Development, Sensory
Sep 18, 2014

PCI Express 4.0 & Controller Design: Veni, Vidi, Vici
This technical webinar reviews key changes in the PCI Express 4.0 specification and explains strategies for dealing with digital design challenges, handling the higher bandwidth, and more.
Richard Solomon, Technical Marketing Manager, Synopsys
Sep 16, 2014

Increase Designer Productivity and Accelerate SoC Design Schedule Through Flow Automation
The complexities of advanced SoC design constantly challenge tape-out timelines. Synopsys' Lynx Design System can simplify and automate flows for many critical implementation and validation tasks, enabling engineers to focus on achieving performance goals. This webinar will introduce you to how customers such as Altera are leveraging Lynx in their design flows to lower risk and improve predictability. Additionally, you will learn about innovative and sophisticated automation solutions for design QoR analysis, correlation and regression that accelerate design schedules.
Lydia Lee, Lynx Design System Staff CAE, Synopsys
Sep 10, 2014

VCS AMS for Advanced SoC Mixed-signal Verification
Learn how ARM and STMicroelectronics are using the advanced verification techniques and productivity features of VCS AMS to verify their mixed-signal SoC designs.
Helene Thibieroz, VCS AMS Product Marketing Manager, Synopsys, Inc.; Pierluigi Daglio, AMS Design Verification Flows Manager, STMicroelectronics; Venkatesh Bharanthi Krishnamurthy, Manager of Design Automation, ARM
Sep 03, 2014

Moore's Cores - Best Practices to Optimize Processor Cores for Performance, Power and Area Targets Specific to Your SoC (in Mandarin)
As silicon capacity continues to grow following Moore's law, so has the growth in computational power. This, along with the complexities of today's designs, has led to the need for multi-processor core SoC's to achieve design goals. Managing the complexity of designs that include CPUs, GPUs, and DSPs in a single chip can be quite challenging. Based upon years of Synopsys' consulting experience implementing hundreds of these SoC's, this webinar will outline design best practices and pitfalls to avoid, to enable you to achieve the right balance of high performance, low power and smaller area.
HuaMin Hou, Senior Design Consultant, Synopsys
Aug 27, 2014

Creating a High-Performance TBE Environment
Transaction-based emulation or TBE has become an increasingly popular method for utilizing emulators because of the high verification performance and flexibility in connecting to existing environments.
Lance Tamura, CAE Manager, Verification Group, Synopsys
Aug 12, 2014

Advanced Mixed-Signal Design and Verification of Smartcar ICs
In this webinar, Micronas and Synopsys discuss the breadth of automotive IC applications, challenges in design implementation and verification and the solutions that stemmed from their collaboration.
Mario Anton, Micronas; Gernot Koch, Micronas; Marco Casale-Rossi, Synopsys
Jul 31, 2014

ProtoCompiler Accelerates HAPS FPGA-Based Prototyping Systems
This webcast examines the latest generation of design tools for prototyping, Synopsys ProtoCompiler, a suite of design automation and debugging tools for the Synopsys HAPS Series of FPGA-based prototypes.
Troy Scott, Product Marketing Manager, Synopsys
Jul 23, 2014

FinFETs For Your Next SoC: To Move or Not To Move?
Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare embedded memory and logic library IP can enable this move.
Prasad Saggurti, Product Marketing Manager for Embedded Memory IP, Synopsys
Jul 22, 2014

Verifying Clock Domain Crossings in Complex SoCs – Are You Sure You Caught All the Bugs?
Avoid missing a CDC bug that causes a silicon re-spin! The Synopsys VC CDC solution provides comprehensive CDC verification at RTL for any size design, up to and including SoC full-chip flat, enabling designers to find and debug CDC issues early in the design cycle. We’ll discuss why our solution will find bugs that purely hierarchical solutions will miss, and do so with far less designer impact than any other solution.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Namit Gupta, Corporate Application Engineer (CAE), Verification, Synopsys; Kaushik De, Scientist at Synopsys, Design Verification, Synopsys
Jul 16, 2014

Designing with Non-Volatile Memory for High-Volume Automotive ICs
Learn about the challenges with designing high-volume automotive ICs and the associated non-volatile memory requirements for high performance, high reliability, and optimized area.
Angela Raucher, Product Line Manager, Synopsys; Martin Niset Senior R&D Manager, Synopsys
Jul 15, 2014

Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014

Achieving Ultra-Low DPPM: Avago Case Study
Hear experts from Avago and Synopsys describe key advanced fault models available in Synopsys' synthesis-based test solution, DFTMAX and TetraMAX ATPG, to achieve ultra-low DPPM.
Stefano Zanatta, DFT Engineer, Avago Technologies; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Jun 26, 2014

Automate ASIC to FPGA-based Prototype Conversion with Synplify
Using Synplify, automate ASIC to FPGA-based prototype conversion to accelerate fast FPGA-based working prototype bring-up, debug and validation.
Dr. Angela Sutton, Staff Product Marketing Manager, FPGA Implementation, Synopsys
Jun 18, 2014

Advanced-Node Variability Characterization and STA Margining with SiliconSmart and PrimeTime
Learn about the new slew-/load-dependent POCV delay model, and hear GLOBALFOUNDRIES describe their experiences using SiliconSmart and PrimeTime to implement a variation-based methodology for advanced
Dr. Tamer Ragheb, SMTS Design CAD Engineer, GLOBALFOUNDRIES; Moninder Bansal, Senior Manager, Corporate Applications Engineering, Synopsys
Jun 11, 2014