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News
Synopsys Delivers 2X Speedup for Implementing and Verifying Functional ECOs
Synopsys Announces Design Kit Optimized for All SoC Processor Cores
Synopsys Unveils New Synthesis-Based Test Technology Delivering Up to 3X Higher Compression
Synopsys Delivers Comprehensive Design Implementation Solution for Samsung's Leading-Edge 14-Nanometer FinFET Process
TSMC Certifies Synopsys' Digital and Custom Solutions for 16-nm FinFET Process
Synopsys Introduces Starter Kit for DesignWare ARC EM Processors
Synopsys Delivers VDK for Renesas RH850 MCUs
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Analog Insights
A View from the Top: A System-Level Blog
Absolute Power
Breaking the Three Laws
Configurable Thoughts
Conversation Central Podcast
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Webinars
VCS Constraint Debug
Increasing the Productivity of Mixed-Signal Verification and Debug Using CustomExplorer Ultra
Custom Layout Using the Laker Custom IC Solution
Verilog-to-Verilog Equivalence Checking Using ESP
Samsung and Synopsys share their perspective on 14-nm FinFET design
TSMC and Synopsys Present: DFTMAX Compression, Hierarchical Test and iJTAG
Transaction Debug with Verdi3
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D43D 2013 Design for 3D Silicon Integration Workshop
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A
AMBA Fabric and Peripherals
AMS Co-Sim
ARC Processor Cores
Architecture Design Models
Audio IP
C
Camelot
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Certify
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CHIPit
Circuit Check
CODE V
CoMET/METeor
CoMET/METeor Models
coreAssembler
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coreConsultant
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D
Data Converters
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DC Ultra
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Design Compiler Graphical
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DesignWare IP
DesignWare TLM Library
DFTMAX
E
Embedded Memories
ESP-CV
Ethernet
Ethernet IP
F
FineSim
Formality
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FPGA-Based Prototyping
G
Galaxy Constraint Analyzer
H
HAPS
HDMI IP
Helix
Hercules
HSIM
HSPICE
I
IC Compiler
IC Validator
IC Workbench Plus
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J
JPEG
L
Laker Blitz
Laker Custom Design
Laker Flat Panel Display
Laker Test Chip Development
Leda
Liberty NCX
LightTools
Logic Libraries
Lynx Design System
M
Magellan
Manufacturing
Memory Models
Memory Test and Repair
Microcontrollers
minPower Components
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M
Mobile Storage
MVRC Multi-voltage Rule Checker
MVSIM
N
NanoTime
Non-Volatile Memory
O
Odyssey
Optical Engineering Services
P
PA/Virtual Prototyping
PCell Xtreme
PCI Express
PCI/PCI-X
Pioneer-NTB with Vera
Platform Architect
Power Compiler
PrimeRail
PrimeTime
PrimeYield
Process Simulation
Processor Designer
Proteus
Proteus MetroKit
ProtoLink
PSM-Check and Create
PyCell Studio
Q
QuickCap NX
R
Raphael
S
Saber
Saber Harness
Saber Simulator
SATA
Seismos CX
Seismos LX
Sentaurus Device
Sentaurus Interconnect
Sentaurus Lithography
Sentaurus Process
Sentaurus Topography
Signoff
SiliconSmart
Siloti
SPW
SPW Model Libraries
Star IP
StarRC
Synphony C Compiler
Synphony Model Compiler
Synplify Premier
Synplify Pro
System Studio
System Studio Libraries
SystemC TLM Models
System-Level Models
SystemNav
T
Talus Vortex
Taurus-Medici
Taurus-TSuprem4
TCAD
TetraMAX ATPG
Titan Accelerators
Touch Screen Controller IP
U
USB
V
VCS
VCS Verification Library
Verdi
Verification
Verification IP
Video Analog Front Ends
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X
XAUI IP
Y
Yield Explorer
YieldManager
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