Synopsys Insight 

2012 Past Issues 
Issue 4 - 2012
Using Advances in Synthesis Technology to Cut Implementation Time
The Past, Present and Future of DDR4 Memory Interfaces
Accelerate Software Development with High-Performance FPGA-based Prototyping
Complete Audio Solutions with ARC Processors
Improving Compute Farm Efficiency for EDA
Accelerating SoC Verification
Latest News on Products, Technologies, Services and Solutions to Help Accelerate Innovation
OpenStand: Measuring up in Design Automation Standards
Ace the Verification of Multicore SoCs

Issue 3 - 2012
- Achieving Faster Design Closure with Early RTL Exploration
- Managing Design Density for Improved Manufacturability and Faster Closure at Advanced Nodes
- FinFET: The Promises and the Challenges
- Next-Generation Xilinx FPGA Flows: Gaining Success Using Synopsys Tools with Xilinx Vivado Place-and-Route Software
- The Benefits of Static Timing Analysis-Based Memory Characterization
- Building High-Performance Interfaces for Storage, Camera and Displays Using UniPro and UFS Controller IP
- Virtual Prototyping Goes Mainstream
- Building an IP-XACT Design and Verification Environment with DesignWare IP
- A Simple Way to Use DesignWare Libraries in FPGA-Based Design Prototypes
- Video Interview with Frank Lee – An Introduction to FinFET Design Tools
- Latest News on Products, Technologies, Services and Solutions to Help Accelerate Innovation
- Global Standards Development Requires Sound Fundamentals
- Connect with Experts at VIP-Central.org

Issue 2, 2012
- Get a Head Start: Early Software Bring-up for ARM big.LITTLE Processing
- Delivering Great Audio with an SoC-Ready IP Subsystem
- The Best of Both Worlds for SoC Prototyping
- Low Power is Everywhere
- A Perspective on How Standards are Enabling 'Better, Sooner, Cheaper' Designs
- Latest News on Products, Technologies, Services and Solutions to Help Drive Differentiation and Innovation
- Peace, Love and Interoperability in the EDA Standards World!
- Tap into SNUG 2012 – Your Global Design Community Focused on Innovation
- Calling all Automotive Electronics Designers – Check out Synopsys' NEW Automotive Technical Bulletin

Issue 1, 2012
- Combining Tools and Technology for 20nm Gigascale ICs
- Discovery: A New Generation of Verification IP
- A Silicon Interposer-based 2.5D-IC Design Flow, Going 3D by Evolution Rather than by Revolution
- Constraint Analysis Makes For More Predictable Tapeout
- The Fast Track to 3D-IC Testing
- Industry Initiatives: Discovery Verification IP
- Latest News on Product Updates, Technologies, Services and Solutions
- Do Standards Matter to Users? You Bet!