Synopsys Insight Newsletter 

Insight Home   |  Previous Article   |   Next Article

Issue 3, 2012

Partner Highlight:
Managing Design Density for Improved Manufacturability and Faster Closure at Advanced Nodes

IC designers are familiar with dummy fill as a requirement for improving the planarity of wafers and die and enhancing overall lithographic error margin. At 28-nanometers (nm) and looking beyond, uniform planarity requires many complex design density rules and constraints. Furthermore, fill shapes are closer to active signal nets than ever before, increasing coupling capacitance variability and presenting risk to timing closure. Based on a recent study on 28nm fill at AMD, Stelios Diamantidis, product development and commercialization of physical verification technologies, Synopsys and Norma Rodriguez, principal engineer, design-for-manufacturing (DFM), AMD, discuss the challenge of density management and introduce Fill-to-Target (or FTT) technology in IC Validator, Synopsys’ physical verification platform. FTT manages density as a key design consideration, delivering optimal uniformity even around prefilled macros. Coupled with IC Compiler In-Design technology, FTT curtails coupling capacitance build-up due to fill, eliminating late-stage surprises and accelerating manufacturing closure.

Planarity – Isn’t it the Foundry’s Problem?
Density management became critically important in the 1990s to enable Chemical Mechanical Polishing (or Polarization), a term commonly known in the industry as “CMP”. CMP is the semiconductor manufacturing process of smoothing surfaces with the combination of chemical and mechanical forces. This process removes excess material from the surface of a wafer, evening out irregularities and rendering the wafer more flat, or planar. The primary objective of CMP is to bring the entire surface of the wafer within the depth-of-field accuracy requirement of a photolithographic system. CMP also improves structural integrity and enables even distribution of stress across several layers within the integrated circuit.

Although traditionally a fab-side challenge, CMP has come to impact semiconductor design significantly. To ensure good planarization, incoming designs needed to have both adequate layout density and smooth distribution. Hence, “dummy” fill techniques were created to manage density by adding non-functional shapes to the layout as a chip-finishing step. However, as deep-submicron process technologies continue to deploy a 193nm light source and rely heavily on computational lithography, depth-of-field accuracy requirements have reached Angstrom levels. In this environment, even tiny abrasions and impurities during CMP can prevent material removal in a uniform and predictable fashion, resulting in systematic yield loss. Fill techniques have therefore had to evolve in order to deliver to an increasingly stricter quality of result (QoR) for manufacturability.

At 28nm, and looking beyond, the traditional methodology of design post-processing for density and manufacturability has run out of steam. First, designers are finding it very difficult to comply with the ever more complex foundry rules and requirements (Table 1). Changing density specifications as needed on a per design basis, adding specialized rules, and considering multi-layer interaction effects are all placing excessive stress on the traditionally ad-hoc process of design post-processing for fill.

Foundry density management requirements
Table 1: Foundry density management requirements

Second, as geometries shrink, fill shapes are placed closer to active signal nets than ever before, causing increasing coupling capacitance build-up and introducing risk of late-stage timing surprises.

Traditional fill methodology. Fill is inserted as a post-processing step after timing and DRC closure.
Figure 1: Traditional fill methodology. Fill is inserted as a post-processing step after timing and DRC closure.

As shown in Figure 1, fill insertion traditionally occurs after timing closure has been reached and the design is DRC (design rule check) clean. Designers hence need to acknowledge that inserting fill as part of this flow will expose their design to coupling capacitance variability and will definitively influence timing.

In summary, density and timing are both very key and often competing design requirements. Achieving optimal design quality and manufacturability while avoiding late-stage surprises requires a fresh approach to fill, one that:
  1. Manages the many constraints of foundry density requirements in a streamlined manner
  2. Balances density and timing for designer productivity and faster design closure

Fill-to-Target: A Better Way to Manage Design Density
IC Validator 2012.06 introduced new Fill-to-Target technology, or FTT. The result of a multi-year collaboration with IDM and foundry partners, FTT represents a fresh approach to density management, targeted at making the fill process more result-oriented, predictable, and designer-friendly.

Managing Foundry Density Requirements
The foundation of a smarter approach to density management is to “begin with the end in sight.” Fill tools usually rely on foundry rules, which largely regulate spacing and local density. FTT expands this scope to offer a constraint-driven approach, based on tile-based layout analysis and parametric, close-loop, fill flow (Figure 2).

FTT tile-based analysis. A programmable grid of tiles is applied to allow local characterization of layout data.
Figure 2: FTT tile-based analysis. A programmable grid of tiles is applied to allow local characterization of layout data.

A programmable grid of tiles is applied to allow local characterization of layout data. Parameters of interest, such as density, perimeter, and others, are captured into a parametric layer. This parametric data is used to drive intelligent fill creation algorithms that deliver to multiple constraints both locally and globally. This closed loop analyze-fill approach allows the tool to make cost-based decisions and identify the right fill shape for the right space, boosting QoR and eliminating late-stage surprises related to design density (Figure 3).

FTT closed-loop fill insertion uses parametric data to insert the right shape in the right place.
Figure 3: FTT closed-loop fill insertion uses parametric data to insert the right shape in the right place.

The FTT approach is particularly effective when considering filling around pre-filled IP blocks (hard macros), a typical source of late-stage density violations. FTT delivers smooth gradients around macros by allowing engineers to supply relevant parametric information up front. This way, IP block parameters can be factored into the analysis of adjacent tiles, giving FTT all necessary information to ensure that a single-pass flow can satisfy user requirements.

In a 2012 study, AMD compared FTT to the more traditional fill insertion used in production at the time (“Plan of Record – PoR fill”) (Figure 4 and Figure 5). The study compared a variety of metrics related to overall QoR and turnaround time performance.

FTT-generated fill for an AMD 28nm design (Metal 3 layer). A variety of shapes and orientations is used to meet density goals, while maintaining tight distribution of material for improved manufacturability.
Figure 4: FTT-generated fill for an AMD 28nm design (Metal 3 layer). A variety of shapes and orientations is used to meet density goals, while maintaining tight distribution of material for improved manufacturability.

AMD 2012 Study – Comparing median density of traditional PoR fill vs. FTT. <br />The target density of 45% was readily met within expected tolerance.
Figure 5: AMD 2012 Study – Comparing median density of traditional "PoR" fill vs. FTT. The target density of 45% was readily met within expected tolerance.

AMD’s results clearly demonstrate the benefit of adopting the FTT approach for density management and manufacturability. Median density across all metal layers met the density target within acceptable tolerance for local effects. FTT’s fine grain accuracy allowed AMD to raise the overall density goal for metal layers to 45%, and limit the min/max range between 35% and 70%.

Performance results were equally impressive. FTT delivered 2x faster overall runtime compared to AMD’s PoR fill, while also eliminating late-stage iterations related to density window violations. Size of fill on disk increased but this increase was anticipated given the broader range of fill shapes involved and higher overall density compared to PoR fill.

AMD 2012 Study – Comparing performance of traditional PoR fill vs. FTT. <br />Faster runtime and equivalent memory utilization/size on disk (normalized for improved QoR).
Figure 6: AMD 2012 Study – Comparing performance of traditional "PoR" fill vs. FTT. Faster runtime and equivalent memory utilization/size on disk (normalized for improved QoR).

Given the observed benefits, AMD decided to standardize on IC Validator Fill-to-Target as their new production density management system at 28nm.

Balancing Density and Timing Requirements to Preserve Timing Closure
Meeting density challenges within schedule requires elevating fill to a key design consideration, rethinking traditional design flows and methodologies. Extracting for and preserving timing, managing hierarchy, data representation, integration in the design flow, and ECO handling are all important aspects of making fill insertion more designer-friendly. A better approach to density management should intelligently bring foundry signoff accuracy into the design environment, enabling hierarchical fill within place-and-route tools and making fill visible to downstream parasitic extraction and signoff engines. This type of step-up in designer productivity cannot be achieved by point tools alone; it requires smart integration and carefully crafted design flows.

To efficiently balance manufacturing requirements with the traditional designer care-abouts of area, power, and performance, IC Validator is intelligently integrated with IC Compiler for In-Design physical verification. The In-Design approach enables bringing together key elements of these independently optimized tools to address complex problems efficiently and eliminate wasteful fix-verify iterations (Figure 7).

In-Design physical Verification for density management. The bottom-up approach makes it possible to handle fill insertion as part of overall design evolution.
Figure 7: In-Design physical Verification for density management. The bottom-up approach makes it possible to handle fill insertion as part of overall design evolution.

Combined with FTT, In-Design technology enables a more bottom-up approach to density management:
  • a) Fill is done at each level of construction of design building blocks
  • b) Density validation becomes part of signoff for each block
  • c) There are multiple opportunities to customize fill to different needs
  • d) Fill insertion can be timing-aware, protecting sensitive areas from parasitic variability
  • e) ECO cleanup can be automatically handled with nominal impact to the design

The In-Design approach makes it possible for engineers to balance density and timing more efficiently, minimizing impact due to coupling capacitance build-up. First, the effects of fill on parasitics and timing become visible to the design environment, boosting correlation with final signoff. Second, In-Design technology makes it possible for IC Compiler and IC Validator to share design timing information. This information is then used by IC Validator during the FTT process to automatically ensure proactive handling of fill shapes around critical timing areas, for both same and adjacent layers (Figure 8). Trade-offs become metric-driven and any conflicts are resolved within the tolerance requirements of both manufacturing and timing closure. The timing-aware flow eliminates not only late-stage surprises, but also unnecessary iterations between design teams and with downstream analysis tools.

Timing-aware fill insertion within IC Compiler. Left: Non timing-aware. Right: Timing-aware. Spacing to fill shapes on same and adjacent layers is automatically increased around critical paths to minimize variability.
Figure 8: Timing-aware fill insertion within IC Compiler. Left: Non timing-aware. Right: Timing-aware. Spacing to fill shapes on same and adjacent layers is automatically increased around critical paths to minimize variability.

As part of their 2012 study, AMD examined the impact of coupling capacitance variability due to fill on high-performance design timing at 28nm (Figure 9).

AMD 2012 Study – Effect of fill on high-performance design timing.
Figure 9: AMD 2012 Study – Effect of fill on high-performance design timing.

In AMD’s testcase, Worst Negative Slack (WNS) impact due to fill was 7ps, a significant change for high-performance design. In-Design timing-aware fill was able to contain the change to 3ps, saving valuable margin. It is also important to consider that the WNS metric captures the single worst path. It was determined that this path appeared in a fairly dense area of the design, which FTT treated with a relatively moderate number of fill shapes. Otherwise, the impact to WNS could have been more severe.

The Total Negative Slack (TNS) metric was also quite telling. The impact of fill on timing when it came to total slack was measured at 24%, with multiple paths becoming of concern to designers. However, in the case of In-Design timing-aware fill, TNS impact was reduced to 6% and no paths showed any notable new risk to timing closure. In addition, there was negligible difference in design density and performance metrics, leading to the conclusion that density and timing balance was successfully maintained.

Conclusions
At 28nm, and looking beyond, the traditional methodology of design post-processing for density and overall manufacturability can lead to suboptimal results and schedule delays. This paper presented a novel approach to density management based on new Fill-to-Target technology in IC Validator and In-Design physical verification with IC Compiler. Proven at AMD for high-performance physical design at 28nm, Fill-to-Target makes it possible to more efficiently balance manufacturing and timing requirements, delivering better density while accelerating design closure.



More Information:


About the Authors
Stelios Diamantidis manages product development and commercialization of physical verification technologies at Synopsys, focusing on integration strategies with physical design. He has more than 15 years of experience in engineering, management and marketing of software products for the semiconductor industry. Stelios holds a M.S. in Electrical Engineering from Stanford University, California.

Norma Rodriguez is a principal design engineer at AMD, with over 20 years of diverse experience. She is currently the technical lead for managing manufacturing compliance in physical design flows for microprocessors and graphics ICs. She has done extensive work in improving backend yield by injecting DFM rules in router environments as well as custom layouts. Norma was the recipient of AMD’s Corporate Technical Award for her innovative work with DRC+ technology. She holds a B.S. degree in Mathematics and Physics from the National University of Lima, Peru.


Acknowledgments

The authors would like to acknowledge the invaluable contributions of many colleagues who helped with conducting the study, including Jie Yang and Ed Roseboom at AMD; Maheshwar Sivadhiswar, Dan Marolda, Prashanth Yalamanchili and Elango Velayutham at Synopsys.


Having read this article, will you take a moment to let us know how informative the article was to you.
Exceptionally informative (I emailed the article to a friend)
Very informative
Informative
Somewhat informative
Not at all informative