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Issue 1, 2013

The following article was originally published in Synopsys’ DesignWare Technical Bulletin.

Technology Update
Embedded Memory Test & Repair at 20-nm Nodes and Below

With embedded memories dominating the SoC area in today’s designs, SoC yield relies heavily on memory yield. In order to meet the stringent requirements of next-generation, high-performance devices, these designs must be larger and use multiple processor cores. The increased design complexity presents a unique set of test and yield challenges including higher test costs, yield implications due to a higher total bit count, higher power consumption during test, and lower design productivity. Additionally, there is greater manufacturing complexity in 20-nm technology nodes, which create new yield challenges, both in the form of increased defect densities and in the form of new types of failure mechanisms that need to be modeled for accurate detection, diagnosis, and repair. It is essential to have an embedded memory test and repair solution that not only meets the above challenges for today’s designs, especially those at 20-nm and below, but that is also cost-effective.

This article provides an overview of the newly released DesignWare® STAR Memory System® 5 to specifically address the challenges of designs on 20 nm and below.

Overview
Synopsys’ DesignWare STAR Memory System is a comprehensive and fully automated solution to test, repair, and diagnose embedded memories from Synopsys as well as from any 3rd party. Now in its 5th generation, STAR Memory System 5 provides a complete solution for designs with high complexity and/or those implemented at advanced process nodes. Some of the key features of the solution are:
  • Automated test and repair IP creation, hierarchical SoC insertion, integration, verification, and tester-ready pattern generation and analysis
  • Full test algorithm programmability during design as well as post-silicon stages
  • Efficient on-chip self-repair operating under multiple corners to optimize yield
  • Protection against soft errors with multi-bit upset error correcting codes (ECC)
  • RTL/gate-level solution for memories from Synopsys and any 3rd party
  • Advanced failure diagnosis with physical failed bitmaps and XY coordinates of failing bit cells

STAR Memory System
Figure 1: DesignWare STAR Memory System 5: STAR Memory System comprises infrastructure IP including wrappers to provide memory access during test, SMS processors to perform test, diagnosis and redundancy analysis, and an SMS server to control and schedule memory test through the SMS processors

Performance- and Area-Optimized Architecture
STAR Memory System 5 comes with a new enhanced architecture to efficiently test, repair, and diagnose thousands of embedded memories. It provides a 30 percent reduction in area investment compared to the previous generation while enabling faster design closure. This reduction in area is the result of efficient test-generation logic, which stores programmable test algorithms in an optimized way. In addition, the new version offers a daisy chain, or ring, configuration in which multiple SMS processors are configured to connect to the SMS server, as shown in Figure 2. This daisy chain configuration provides significant savings in the signal routes compared to the previous approach in which all the SMS processors connected directly to the SMS server. There is no restriction on the number of processors per ring or the number of rings that that can connect to the SMS server. The rings can be based on the physical hierarchies (subchips), power domains, or other design-specific needs. This ring configuration provides up to a 15 percent reduction in routes.

STAR Memory System
Figure 2: Hierarchical Ring Configuration in STAR Memory System 5

To ensure minimal performance impact of built-in self-test (BIST) MUXes inserted into a functional path, the STAR Memory System is able to reuse any existing pipeline stages on the function path to a memory. Also, the STAR Memory solution allows the addition of any number of pipeline stages needed to meet a design’s at-speed memory testing requirements. The pipeline stages are user configurable and are added between the test and repair IP blocks, i.e. SMS processors and wrappers.

STAR Memory System
Figure 3: Configurable pipelines to meet at-speed test requirement

As with the previous generation, the latest version of the solution provides a unique advantage when used with Synopsys memories in that the timing-critical part of the STAR Memory System logic is hardened along with the memory hard macro, providing higher functional performance, at-speed memory test and ATPG coverage, while reducing the memory subsystem area and power.

High-Performance Processor Core Support
High-performance processors with embedded caches need a memory test and repair solution that will not impact processor performance. To avoid the additional BIST MUX delay added by memory test solutions, processor core providers such as ARM are adding the required test structures (e.g. MUXes and pipeline flops) at optimal positions inside the core. This minimizes the impact on functional timing and brings the required test signal as a multi-memory bus at the processor core level. The STAR Memory System uses this bus to test and diagnose memories without adding any additional BIST MUXes or wrapper logic on the memory paths. Instead, it adds memory embedded test and repair logic in the form of the SMS processor outside the processor core to avoid any impact on processor performance (Figure 4).

STAR Memory System
Figure 4: STAR Memory System 5 support for ARM processor cores with integrated BIST bus

Test Algorithms for 20 nm and Below
STAR Memory System 5 provides advanced test algorithms for detecting and repairing new types of defects prevalent at 20-nm and below nodes. At 20 nm, there is significant on-chip process variation within the memory cell that affects transistor performance, causing a wide range of failure types. To properly test for process variations, STAR Memory System 5 creates test patterns that are applied across multiple corners. At smaller geometries, small delay defects are more common and small delays in address decoders can generate incorrect results. STAR Memory System 5 provides advanced memory addressing to specifically detect the address decoder faults. It also allows programmability in a wide range of test resources to allow the creation of custom algorithms for test, characterization, or diagnosis purposes.

Advanced Diagnostics
Having a good diagnostic solution is a must for achieving faster yield ramp and time-to-volume. The need is much greater at 20-nm and below technology nodes as the yield ramp is relatively slower due to increased defect densities and new defect types. STAR Memory System offers advanced diagnostics capabilities for rapid and accurate fault isolation and classification. The solution provides more than seven levels of resolution for failure analysis including the logical/physical failed bitmaps and XY coordinates of failing bit cells. In addition the STAR Memory System provides a library of high-resolution diagnostic algorithms that can be used for diagnosing specific fault types. The user can generate tester ready patterns in standard WGL, STIL, or SVF formats avoiding the need for simulations or translations.

STAR Memory System
STAR Memory System
Figure 5: STAR Memory System 5 Diagnostics Flow

Conclusion
An efficient embedded memory test, repair, and diagnostics solution is essential for achieving high SoC yield, especially at advanced process nodes. At the same time, the solution needs to minimize the design cost (silicon area, implementation effort) and test cost (test time, test quality, silicon debug and diagnosis time). Synopsys’ DesignWare STAR Memory System provides a comprehensive solution for embedded memory test, repair, and diagnosis to optimize SoC yield, while meeting overall cost, quality, and schedule goals.


More Information

About the Author
Sandeep Kaushik is the Sr. Product Marketing Manager for the Embedded Memory Test and Repair product line at Synopsys. Sandeep brings over 12 years of experience in the field of Design-for-Test. Sandeep holds a Bachelor's Degree in Electrical Engineering from the Indian Institute of Technology in Delhi, India and a Master's Degree in Electrical Engineering from Stanford University. He is currently working towards his Master's Degree in Business Administration from the Haas School of Business, University of California, Berkeley.


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