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Issue 3, 2012
Building High-Performance Interfaces for Storage, Camera and Displays Using UniPro and UFS Controller IP
Hezi Saar, staff product marketing manager, Synopsys, highlights Synopsys’ new IP for storage, camera and display interfaces: DesignWare® UFS and UniPro controllers. Deployed on top of Synopsys’ M-PHY physical layer, the new IP offers design teams a complete, single-vendor solution for UFS connectivity and UniPro-based protocols supporting the JEDEC UFS v1.1 interface specification.
Today’s mobile systems place increasingly higher demands on chip-to-chip interfaces transferring data and multimedia content between components. High-resolution displays, megapixel cameras and the need to store the data that these advanced systems produce means that it’s not unusual for design teams to have to implement multiple “gigabit” chip interfaces. Fortunately, the developers of the M-PHY specification, as well as UniPro and UFS protocols, had low-power and high-speed operation in mind when they specified the latest protocols--which helps for multiple high-speed interface applications.
Synopsys has been working with the standards bodies behind UFS (JEDEC) and UniPro (MIPI Alliance) for several years to help enable the evolution of the protocols. The specification for UniPro is extremely complex, and to implement UniPro well, it is essential to understand the application space as well as the function of the protocol.
- Our UniPro controller IP was developed with potential applications in mind and as a result, the highly configurable Synopsys DesignWare UniPro IP can support different applications on the host or on the device side, including:
- Mobile storage devices using UFS
- Display ICs using DSI-2
- Image sensors using CSI-3
Being able to service all of the UniPro-based protocols from a single vendor helps design teams reduce integration risk and meet their time-to-market requirements. The UniPro controller can be used as a platform to implement the application layer (e.g., a CSI-3 device for image sensor ICs) to maintain a company’s differentiation.
Both UniPro and UFS implementations can be deployed on Synopsys’ small footprint, low-power and future-proof MIPI M-PHY IP, which we introduced in early 2012. The M-PHY supports data rates between 1.25 Gbps and 5.8 Gbps and up to four receive and four transmit lanes. Other features include power-efficient clock generation for high- and low-speed clocks, and built-in diagnostics and ATE functionality for improved testing. Synopsys’ M-PHY is compatible with M-PHY Type I or II M-PORT, supporting the standard RMMI interface to the protocol layer, which is the de-facto standard interface for LLI, SSIC and UniPro.
The industry expects future enhancements in mobile interfaces to demand even higher speeds, which is why the Synopsys M-PHY supports the High Speed Gear3 rate of up to 5.8 Gbps. Many design teams want to future-proof their designs by investing in IP that can support protocol enhancement and extensions to higher speed, instead of adding lanes.
UniPro Controller Features
The UniPro Controller (Figure 1) includes a PHY adaptation layer and data link layer, while network and transport layers provide interconnect to the M-PHY via a standard RMMI interface. It also incorporates an easy-to-use interface to the application layer including read and write interfaces via C-ports, and a configuration interface to the DME.
Figure 1: UniPro controller architecture overview
- To meet the needs of a specific application, design teams can customize the DesignWare UniPro Controller by configuring the following parameters:
- Number of C-ports (1 - 2048) and data width (16, 32, 64, 128-bit)
- Number of Rx and Tx lanes to M-PHY (range 1-4)
- Tx and Rx buffer depths
- All traffic classes
- Number of L4 test features
- DDB settings
- Key features of the UniPro IP include:
- Compliant to MIPI UniPro specification v1.41
- Structured into layers defined by the specification
- Application layer can be implemented on top of UniPro (like UFS)
- C-Port Write interface to send to remote device
- C-Port Read interface to receive from remote device
- Configuration interface to program all layers (DME)
- M-PHY adaptor layer interfaces with M-PHY via RMMI
We have designed the UniPro Controller to help development teams reduce complexity when creating their designs. The Synopsys IP handles the dataflow and the datastream going back and forth from the media (M-PHY) to the application layer to simplify the application implementation. The UniPro Controller manages the complexity in the protocol itself, while maintaining reliability through an intelligent application-specific implementation.
UFS Host Controller Features
The UFS Host Controller incorporates both the UniPro Controller and the UFS Host application layer, and has multiple interfaces to the SoC. The UFS Host Controller incorporates a pre-instantiated UniPro controller that is optimized for a UFS Host application.
The UFS Host Controller manages the protocol between the host and the storage device, sending all the commands and managing storage both in and out.
Figure 2: UFS Host Controller architecture
Figure 3 shows a typical system configuration. The box at the top of the diagram represents the host processor and the bottom box is the storage IC.
Figure 3: Use of UFS host and UniPro controllers in a typical system configuration
Synopsys provides the IP components shown on the right side of Figure 3. Design teams for UFS storage devices can differentiate their designs by creating their own UFS device controllers, while making use of a proven UniPro and M-PHY IP from Synopsys.
As time-to-market pressures continue, design teams want to validate their SoCs working together with other devices by taking advantage of hardware prototypes. Synopsys’ HAPS® FPGA-based prototyping system meets this need and incorporates a UniPro Controller or UFS Host Controller. The ability to easily test interoperability between system components, using proven controllers and PHY components, helps to reduce risk and speed time to market.
Synopsys helps customers accelerate their design cycle by providing a proven UniPro-based prototyping platform that can be used for UFS implementation or future protocols such as CSI-3 and DSI-2.
Collaborating for Low Risk
Creating complex IP based on industry standards requires close collaboration with industry partners.
Synopsys works closely with foundries to ensure that our development aligns with their roadmaps and latest process nodes. We work with test equipment manufacturers to ensure that their products work with the latest implementation of the specification, and to enable them to test their own implementations using our IP solutions. We supply the semiconductor vendors that are used in mobile devices, which, in effect, determine the pace of adoption of standards.
We also work with all of the peripheral and component vendors to ensure that our IP is compatible with their image sensors, storage devices, displays, and RFICs.
The use of pre-designed, configurable IP, including M-PHY IP, enables design teams to create high-performance chip-to-chip interfaces between host processors and device ICs with reduced risk. Synopsys delivers a complete UFS Host solution and makes a UniPro-based platform available for vendors to develop the application layer. By maintaining control of the application layer of the device IC (e.g., storage or image sensor) interfaces in-house, design teams can ensure that they differentiate and add value to their overall solutions.
Building on the future-proof M-PHY IP, we have added DesignWare UFS and UniPro IP for a complete, single-vendor solution (including hardware prototyping) that includes all functions needed for high-reliability UniPro-based protocols and JEDEC UFS connectivity.
With DesignWare UFS and UniPro IP, system architects have access to a complete, fully interoperable and proven solution, all from a single IP vendor.
The UniPro controller offers application-optimized implementation for all host and device storage (UFS), camera (CSI-3) and display (DSI-2) applications. Both the UniPro v1.41 and UFS v1.1 controller IP are available now.
Figure 4: Complete IP solutions for rapidly expanding MIPI protocol markets
Synopsys’ expanding IP portfolio can cover most of the application needs in today’s application processors. As well as providing PHYs and controllers, our IP solutions include verification IP, sample software that gives developers a head start in building drivers, and boards that enable design teams to prototype their hardware in parallel to the ASIC.
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About the Author
Hezi Saar serves as a staff product marketing manager at Synopsys and is responsible for its DesignWare MIPI controller and PHY IP product line. He brings more than 16 years of experience in the semiconductor and electronics industries in embedded systems. Prior to joining Synopsys, Saar was responsible for Advanced Interface IP at Virage Logic, before it was acquired by Synopsys, and had also served as senior product marketing manager leading Actel's Flash FPGA product lines. Saar holds a Bachelor of Science degree from Tel Aviv University in computer science and economics and an MBA from Columbia Southern University.