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Issue 2, 2012
The following article was published as a Guest Editorial and reprinted with permission from EE Times as part of the EDA DesignLine series on low power.
Low Power is Everywhere
Meeting power budgets for most System-on-Chip (SoC) designs today is no longer a requirement for mobile applications only. Almost every market segment today has some concern with designing in low power features — although the driving factor for why does differ among them. Mary Ann White, Synopsys, explains how different segments have different reasons for making power a primary design requirement.
The primary impetus for low power design was initially driven by the mobile market due to the need for extending battery life; however, different segments do have different reasons for making power a primary design requirement. For example, the advent of the internet and social media heavily drives the Servers and Networking Market segments where large server clouds and compute farms need to work reliably without overheating; so, their primary concern is reducing the amount of expensive energy required for operation and air conditioning. Other markets such as the multimedia and set top box segments are plugged into the wall but ‘green' initiatives and the high cost of electricity have forced them into increasing energy efficiency through building in low power techniques similar to those used in the mobile application space.
- Power is now a primary requirement for all designs – it's not just about performance or area anymore and there are several factors that designers need to take into consideration to meet the stringent low power requirements. There are several key components that comprise a low power design and offer methods for controlling power:
- Technology process selection provides a power vs. performance vs. area tradeoff
- Architectural and implementation techniques offers power vs. complexity tradeoffs
- Optimization engines delivers on rapid time-to-market and quality of results
Even process technologies from semiconductor vendors have had to adapt. It used to be that a low-power (LP) process could be used in place of a generic (G) or high-speed/performance (HS/HP) process to provide significant static leakage savings. Back then, the LP process offered typically a 20-30% slower performance than the standard process in exchange for 1.5X less dynamic and up to 50X less static power dissipation which helped extend battery life in most portable designs.
Nowadays at 28nm and below, there are more process variations targeted for low power to meet the various market demands. LP and HS/HP processes continue to be offered where LP is still targeted for mobile applications and extending battery life. However, there are now process variations in between that offer both performance and lower power depending on the application. For example, TSMC offers a 28nm HPL process technology using high-k metal gates that reduces both operation and standby power by about 40% (vs. HP) which is best suited for cellular, wireless and programmable logic devices. They also offer a 28nm HPM process which offers both high performance and low leakage targeted specifically for mobile consumer applications.
The choices of standard cell library architectures for the targeted process have also expanded quite a bit. There used to only be a single standard cell library architecture (fixed cell height) available per process node – one that is characterized for the different voltage threshold (Vt) points. Now, there are several standard cell height (number of grids) choices that offer performance, power and density tradeoffs. For example, Synopsys offers standard cell libraries that are lower in cell height for consumer applications and taller cells for higher performance applications with examples shown below (Figure 1).
Figure 1: Synopsys DesignWare Logic Libraries Offer Power, Performance and Area Tradeoffs
In addition to the different cell architectures, channel length variants are also available, exponentially increasing the number of actual cell variants available for libraries. Library vendors, like Synopsys, are creating variations of cells with different channel lengths within each cell. Generally, High-Vt (HVt) libraries are better for power and worse for timing, while Low-Vt (LVt) libraries are much better for timing, but are very leaky. With the availability of libraries containing multiple channel lengths, it is possible to achieve better timing and lower leakage with a Standard-Vt (SVt) cell with a longer channel than an HVt cell with standard channel length. As in Figure 2, for the 28nm HPM process, a shorter length SVt cell would provide 17% lower performance and 30% lower leakage than a standard length LVt cell making it more compelling to use while also saving on an extra mask layer.
Figure 2: Power and Performance Tradeoff of Channel Length Variants at 28nm
Starting at 28nm and below, we are seeing the advent of variations of other low power processes such as fully depleted silicon on insulator (FD-SOI) and fin-based field effect transistors (FinFET). FD-SOI can provide high performance with approximately 35% lower power as compared to traditional MOS-based technologies according to ST Microelectronics. FinFET technologies extends the ability to do 3D transistors which offers up to 50% power savings with about 35% better performance compared to traditional planar transistors at 22nm according to Intel.
Architectural and implementation techniques tradeoff power vs. complexity
There are several techniques and architectural methodologies that can be used to provide various degrees of power savings – either dynamically or statically (e.g. leakage). Table 1 shows some of the techniques that can be used to achieve power savings.
Table 1: Low Power Techniques to Save Dynamic and Static Power
Many of these techniques have been around awhile and are mainstream technology such as clock gating and CTS for dynamic power savings, and multi-voltage threshold (multi-Vt) cell library usage for leakage savings. Some of the newer techniques have come about because of the effects of advanced process geometries as discussed in the previous section — for example, final stage leakage recovery takes advantage of using the many channel length/gate bias variations available for the 28nm technology and below processes.
The effectiveness of the power saving techniques can have a tradeoff with design complexity and how easy it would be to deploy in a typical design flow. For example, there is some design complexity tradeoff with the use of biasing – it would require extra routes to the bias taps which can decrease utilization and increase area. This would require a methodology change in addition to supplying different characterized versions of the libraries for more accurate analysis of operation.
Biasing techniques were initially deployed as back-biasing to save in leakage power – this was a particularly effective technique for memories and larger process nodes (>90nm). Body- and source-biasing started to get adopted when some of the smaller geometries provided savings of about 15-25% active leakage at the 90- and 65nm process nodes. But as process nodes continued to shrink towards 20nm, the amount of savings became negligible for traditional MOS-based processes. FD-SOI and FinFET technologies have adapted the use of biasing where the technique may once again become effective.
Synopsys performs a global user survey every year and collects data from the design community that reflects current design trends. Figure 3 shows which of the low power techniques are used across various application market segments confirming the trend that design for power extends beyond mobile applications. Note that respondents were asked to provide all techniques used so the data adds up to more than 100%.
Figure 3: Low Power Techniques Used Across Market Applications
As previously noted, mainstream techniques such as clock gating are prevalent in terms of usage but what is surprising is the high level of adoption of many of the more advanced techniques. Multi-voltage designs (usually driven by standard-based power intent format such as UPF) are now in use by approximately 50% of the respondent's designs. Adoption of these advanced techniques across applications indeed show that design for power is needed everywhere!
Increasing the number of clock domains helps achieve performance and power targets which is also reflected in the user's survey where approximately 30% of the respondents now design with more than 10 clock domains in their designs (Figure 4). Advanced users have reported using up to 1000 different clock domains.
Figure 4: Number of Clock Domains Used in Current Design
In addition to clock domains, the adoption of multi-voltage design is now showing that most designs use anywhere from 1 to 3 different voltage domains operating at different voltage supply levels (Figure 5). More than 30% of the respondents reported that they design with more than 3 different voltage domains.
Figure 5: Number of Voltage Domains Used in Current Design
As part of the global survey, Synopsys asked what are some of the top primary challenges in the design flow with the results shown in the graph below (Figure 6). Timing closure is always the top design challenge, but power management has quickly risen to become #2 where this might not have been included as a primary challenge as recently as 5 years ago.
Figure 6: Top Design Flow Challenges
Synopsys also asked designers to tell us which power management task presented the greatest challenge in their design flow. Since multi-voltage design remains relatively new as an overall power savings technique, it does pose a set of challenges for deployment in a typical design methodology (Figure 7).
Figure 7: Power Management Tasks that Present the Greatest Challenge(s)
Power intent-based flows help automate the implementation of power management techniques. Power intent includes the specification of multiple voltage power domains, power shutdown modes, isolation, voltage level shifting and retention behavior. Power intent is captured as a companion file to the RTL or gate level design using the standardized IEEE 1801 Unified Power Format (UPF). Early definition of power intent in the design flow enables downstream tasks in the process to be automated and driven by a consistent power specification. Used in conjunction with the RTL or gate netlist of a design, UPF is used systematically throughout the design process to describe the design's power intent.
Figure 8: Power Format Usage
Synopsys' global user survey data shows that most digital designers are now using a power intent-based methodology and even more so are planning to deploy it over the next 2 years (Figure 8).
Optimization engines delivers on rapid time-to-market and quality of results
Power is now a primary requirement for almost all designs and is no longer limited to mobile applications anymore. The power techniques will continue to evolve as technology processes continue to shrink and new design challenges surface.
Consumer demand for new gadgets requires rapid time to market with limited product lifespan. The EDA tool selection for developing low power SoCs is based on the ability to deliver the best quality of results (QoR) with predictable results that increase design productivity.
Synopsys' advanced low power solution provides a comprehensive, silicon-proven approach to low power design which includes power-awareness built in at every stage of the design cycle. The advanced low power solution, featuring the Galaxy™ Implementation Platform, offers all of the low power design techniques to deliver maximum power savings. Integrated throughout, Synopsys can increase productivity by providing predictable results early on in the design cycle.
With over 15 years of proven low power innovations, Synopsys will continue to invest in providing advanced solutions for the latest in low power design techniques.
Figure 9: Synopsys' Advanced Low Power Solution
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About the Author
Mary Ann White is the product marketing director for Galaxy™ Implementation Platform products at Synopsys. She has more than 25 years of experience working in the EDA and semiconductor industries. White has a BS EECS degree from UC Berkeley.
View the Original Article: EETimes