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Issue 3, 2012

Technology Update:
Next-Generation Xilinx FPGA Flows: Gaining Success Using Synopsys Tools with Xilinx Vivado Design Suite

Angela Sutton, staff product marketing manager for FPGA Implementation products, Synopsys, explains how Synopsys’ Synplify FPGA synthesis tools complement Xilinx’s new VivadoTM Design Suite for designers seeking more capacity and shorter turnaround times from their FPGA design flows.

The new 28nm 7 Series FPGAs from Xilinx — which includes the low-cost Artix-7, mid-range Kintex-7 and high-end Virtex-7 families – enable design teams to access up to 6.8 billion transistors on a single programmable device. These high-capacity, high-speed All Programmable devices give design teams more options than ever to implement ASIC prototypes and/or production systems that include FPGAs. However, taking advantage of complex programmable devices demands the use of increasingly capable design environments.

Vivado Design Suite for Backend FPGA Design
Xilinx has developed the Vivado Design Suite, an IP and system-centric design environment that boosts developer productivity and enables fast design integration with analytical place-and-route technology, to support design teams working with 7 Series devices and beyond.

When it comes to working with high-end FPGAs, Xilinx recognizes that designers need to draw on flows that combine best-in-class tools for simulation and synthesis, as well as place-and-route. With that in mind, Xilinx has taken a standards-based approach in developing the Vivado Design Suite. The new Xilinx design suite incorporates several standards that are common to Synopsys FPGA and ASIC synthesis flows, including:
  • Synopsys SDC timing constraints (replace proprietary UCF constraints)
  • TCL (for ‘Design Compiler-like’ scripting)
  • Verilog HDL format netlists (replace proprietary or EDIF formats)
  • IP-XACT (for IP packaging)
  • IEEE P1735 (for IP encryption)

By adopting these standards, Xilinx will help ASIC designers more easily migrate between FPGA and ASIC technology for FPGA-based prototyping within their ASIC design flows. ASIC designers are already comfortable with scripting, the use of SDC timing constraints and using encrypted IP, which may be common to both ASIC and FPGA variants of the design.

As well as using common standards, the Vivado Design Suite enables design teams to automatically partition designs across multiple die combined within a single chip using Xilinx’s new 3D-IC stacked silicon interconnect (SSI) technology.

The advanced place-and-route capabilities within the Vivado Design Suite, alongside superior interoperability with other tools and formats, means that design teams will now utilize faster, higher-capacity design flows that they need to be able to incorporate 7 Series devices in their production systems and prototype boards.

Synplify for FPGA Synthesis
Many FPGA design teams around the world already use Synopsys Synplify Pro, Synplify Premier, Certify and Identify FPGA design tools to tackle complex FPGA designs. Those targeting Xilinx FPGAs prior to the 7 Series are using Xilinx’s previous-generation ISE Design Suite to complete the backend stages of the design.

As design teams migrate to 7 Series devices, they will need to move to the Vivado Design Suite for placement and routing of their FPGA design. Synopsys and Xilinx have been working together for over a year to integrate Synplify Pro/Premier with the Vivado Design Suite (Figure 1). Current Synplify users will be able to migrate to Vivado software confident in the knowledge that they can continue to use the Synopsys tools that they know and trust for FPGA synthesis.

Synopsys integration with Xilinx Vivado Design Suite
Figure 1: Synopsys integration with Xilinx Vivado Design Suite place-and-route

Changing Constraint Formats
Design teams used to working with Xilinx’s proprietary UCF constraints will work with Synopsys SDC timing constraints when they migrate to Vivado. Xilinx has phased out the use of UCF constraints. Due to this change, Synplify will not directly read in UCF constraints or Synplicity timing constraints, which will henceforth be referred to as previous constraint formats, in the Vivado flow.

There are both syntactical and conceptual differences between previous timing constraint formats and Synopsys timing constraint formats, and design teams will benefit from understanding these differences so that they can continue to create high-quality and accurate timing objectives for their FPGA designs, and do so more efficiently.

In the past, design teams have often chosen to constrain their designs directly at the place-and-route level. The Vivado flow encourages design teams to specify timing constraints (clocks, I/Os and timing exception constraints) at the RTL level and forward-annotate these constraints alongside the gate-level netlist to the Vivado Design Suite analytical place-and-route tool so that it may continue the endeavour of meeting design objectives. In addition, physical constraints may be provided as input to place-and-route to, for example, guide I/O placement, or assign logic partitions to a specific SSI die within multi-die 7 Series devices. Synopsys provides a graphical constraint editor, SCOPE, which helps designers using Vivado software to more easily create and debug the constraints for their RTL-level designs. Collections and embedded Find and Expand commands may continue to be used without worry within the RTL level constraints specification.

There are also other, more subtle differences between the constraint formats. For example, when adopting Synopsys SDC, it’s important to constrain clocks correctly. When you define a Synopsys SDC clock, it will be assumed to be synchronous with all other clocks. Contrast this to the earlier timing constraint format that could be used as input to Synplify with the ISE flow, where your clocks were assumed asynchronous by default. With Synopsys SDC, particular attention should be given to the specification of clock groupings, or which clocks are synchronous to which other clocks.

Attention should also be paid to whether the clock constraints are being applied to the correct object. When using Synopsys timing constraints, the SDC standard recommends applying a clock constraint to the output port of the clock object. By contrast, prior recommended practice in the combined Synplify and ISE place-and-route flow was
  • Synplify clock constraints could be applied to BUFG instances directly
  • Xilinx ISE place-and-route clock constraints could be applied to nets

It is recommended that designers moving to the integrated Synopsys and Vivado flow convert their clock constraints to follow this Synopsys SDC standard of applying clock constraints to top-level design ports or output ports of clock objects. However, for compatibility purposes, Synplify users continue to be allowed to place constraints on BUFG instances in the Vivado flow. Synplify Premier will simply convert the constraint so that it is applied to the OUTPUT PORT of the BUFG for forward annotation to Vivado place-and-route. For example, if you apply the following Synopsys SDC clock constraint as input to Synplify via the Synplify .FDC file:

create_clock -name {clock_name} [get_cells {clock_0}] -period 50.0 -waveform {0 25.0}

the following clock constraint will be forward annotated by Synplify to Vivado place-and-route via the XDC file:

create_clock -name {clock_name} [get_pins {clock_0/O}] -period {50.0} -waveform {0 25.0}

Also for compatibility purposes, Vivado software will allow clock constraints to be placed on nets.

To make things easier, Synplify provides a translator to help designers do a one-time conversion of files that contain timing constraints in the previous format to equivalent files containing Synopsys SDC timing constraints. Designers will want to then check and manually adjust the converted constraints in the Synplify SCOPE constraints editor.

Synplify Pro and Premier include a constraints checker that helps design teams to validate and debug constraints before they begin the implementation process.

High-End Synthesis for High-End FPGAs
Many design teams use flows incorporating Synopsys Synplify Pro, Synplify Premier, Certify and Identify software for high-end FPGA designs for ASIC prototyping applications and developing production devices. Synopsys’ FPGA solutions offer a number of key benefits to designers tackling high-end designs. These include better quality of results and accelerated turnaround time, faster board bring-up, divide and conquer debug, prototyping automation, and design for high reliability.

Faster Turnaround Time
Synplify-based FPGA flows combine several technologies that can improve turnaround time, which is of particular importance as FPGA sizes are doubling with each new generation of silicon (Figure 2).

Synplify FPGA solutions for faster turnaround time
Figure 2: Synplify FPGA solutions for faster turnaround time

Synplify Premier’s fast mode is a feature that allows designers to accelerate the synthesis process with just a minor impact on quality of results (fast mode spends less time in timing optimization). This may be acceptable – depending on the application and where the design team is in the project lifecycle. Using multiprocessing to enable parallel synthesis also reduces turnaround time, this time with negligible negative impact on QoR. Combining both of these approaches (with a four-CPU multiprocessor) can improve overall TAT by almost 10x compared with not using them. In fast mode and when using multiprocessing, synthesis is guided by timing and design constraints and the software will provide feedback on potential constraints setup issues and on how close you are to achieving design goals. Using fast mode and multiprocessing for quick synthesis spins aids RTL and constraints tuning in order to achieve the function and performance in the final design and can allow quick RTL to board implementation iterations.

The synthesis projects for high-end FPGAs such as the 7 Series devices often include hundreds of source code files from a variety of sources. In order to integrate and troubleshoot large file systems more efficiently, Synplify’s continue-on-error (CoE) feature provides a more complete report of errors with each synthesis pass. CoE allows the Synplify HDL compiler to tolerate non-fatal, non-syntax HDL compilation problems and certain mapping errors in order to analyze and complete as much of the design as possible with each synthesis iteration. Fixes to the errors can be applied incrementally.

Because Synplify FPGA synthesis solutions support the use of hierarchical block-based flows, design teams can construct their designs incrementally, working on one block at a time to design in function and achieve timing closure, instead of having to resynthesize the whole design with each iteration.

This combination of technologies ensures that designs require fewer iterations and teams have access to faster synthesis in order to complete the largest and most complex FPGA designs.

Faster Board Bring-Up
It is not just the scale of Xilinx 7 Series devices that defines the complexity of the design task; it is also that the IP and design files are likely to come from multiple sources. Taking a hierarchical approach is the best way to manage designs of this size and complexity. This allows the design team to divide and conquer, whereby they can use sophisticated debug solutions on individual blocks to diagnose and pinpoint errors. Synplify supports hierarchical design to ensure that design teams can get the device on the board and working much faster than is possible by working on a complete, flat design. Once implemented on the board, the design can be debugged and fixed at the RTL level, using the Identify RTL Debugger.

FPGA-Based Prototyping

Most ASIC design teams conduct FPGA-based prototyping as part of a hardware and software validation strategy (Figure 3). For these kinds of designs it is vital that designers can easily implement the golden ASIC description – ideally without having to manually modify the ASIC source code in order to create the FPGA-based prototype. The designs themselves will include IP such as Synopsys DesignWare Building Blocks, custom source code, as well as timing constraints, and scripts for EDA tool automation.

ASIC flow incorporating FPGA-based prototype
Figure 3: ASIC flow incorporating FPGA-based prototype

Synplify Premier enables designers to migrate the ASIC source code for FPGA-based prototyping by using compiler constraints, a netlist editor, TCL/Find-based scripting, automated gated-clock conversion and the ability to read and implement Synopsys DesignWare IP. Furthermore, design teams can use Synopsys Certify to partition large designs across multiple Xilinx 7 Series FPGAs, manage the FPGA-to-FPGA interconnect, and manage prototype circuit boards.

Design for High Reliability
Design teams must consider chip reliability for a growing range of applications. As well as traditional markets such as aerospace and medical electronics, reliability is of increasing concern for those designing production FPGAs for automotive, communications and some consumer applications.

Synplify Premier synthesis software incorporates a range of features to support preservation of nodes in the design, and probing for debug requirements, to automate ECC RAM inference, and to automate fault-tolerant state machine design. These capabilities enable you to build fault-tolerance into Xilinx designs created with the integrated Synopsys and Vivado flow.

Synopsys and Xilinx have collaborated to create an FPGA design flow that integrates the Synopsys Synplify FPGA synthesis tools and Xilinx’s new Vivado Design Suite. The new flow delivers the capacity and turnaround times that design teams need to get the best out of Xilinx’s latest 7 Series devices.

More Information:

About the Author
Angela Sutton brings over 20 years of experience in the field of semiconductor and semiconductor design tools to her role as staff product marketing manager for FPGA Implementation products at Synopsys. Before joining Synopsys, Ms. Sutton worked as senior product marketing manager in charge of FPGA Implementation tools at Synplicity, Inc., which was acquired by Synopsys in May 2008. Ms. Sutton has also held various business development, marketing and engineering positions at Cadence, Mentor Graphics and LSI Logic. Ms. Sutton holds a BSc. in Applied Physics from Durham University UK, and a Ph.D. in Engineering from Aberdeen University UK.

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